tag: verification

Dynamic in-chip current distribution simulation technology for power device layout design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

Chip Package Co-design and Physical Verification for Heterogeneous Integration
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of each other and integrated along the design cycle. We developed an integration and verification methodology with a physical design driven... » read more

Simulation-Based Fault Analysis for Resilient System-On-Chip Design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover,... » read more

Netlist Decompilation Workflow for Recovered Design Verification, Validation, and Assurance
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Over the last few decades, the cost and difficulty of producing integrated circuits at ever shrinking node sizes has vastly increased, resulting in the manufacturing sector moving overseas. Using offshore foundries for chip fabrication, however, introduces new vulnerabilities into the design flow since there is little to no observability into the manufacturing process. At the same ... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

Two Methods For Debugging SW Workloads On Arm-Based SoCs
By Andy Meier - 11 Nov, 2021 - Comments: 0

By Andy Meier and Tomasz Piekarz In a typical system-on-a-chip (SoC) development project, chip architects will make a given SoC's initial specification available to design teams years in advance of the silicon. As requirements change, they will modify both the hardware and software specifications. Typically, a large portion of the software development occurs much later in the development pro... » read more

How To Reduce The Impact Of The Global Microcontroller Shortage On ECU Software Development
By Siemens EDA - 03 Nov, 2021 - Comments: 0

The COVID-19 pandemic had a massive impact on all facets of business and commerce, as widespread supply chain disruptions rippled through every industry. Multiple factors collided to create a global microcontroller shortage that is now impacting the automotive industry, and is forcing developers to redesign Electronic Control Units (ECUs) using alternative Microcontrollers (MCUs) and to otherwi... » read more

Dealing With Market Shifts
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Back in the days when I was in EDA development, I was taken in by the words of Clayton Christensen when he published "The Innovators Dilemma." He successfully introduced the technology world to the ideas of disruptive innovation. One of the key takeaways was that you should always be working to make your own successful products redundant, or someone else will do it for you. One tool I worked... » read more

What’s Next For Emulation
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

Debug Solutions For Designers Accelerate Time To Verification
By Neil Hand - 28 Oct, 2021 - Comments: 0

Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars. Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Rese... » read more

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