tag: verification

New Design Approaches At 7/5nm
By Ed Sperling - 04 Mar, 2019 - Comments: 0

The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Formal Verification Of RISC-V Cores
By Sven Beyer - 28 Feb, 2019 - Comments: 0

RISC-V is hot and stands at the beginning of what may be a major shift in the industry. Even a cursory review of upcoming conferences programs and recent technical articles makes that clear. While it is still early in the evolution of the processor architecture, there is certainly the potential that RISC-V will be a game-changer in the IP and semiconductor industry. As “a free and open ISA en... » read more

The Problem With Post-Silicon Debug
By Ann Mutschler - 28 Feb, 2019 - Comments: 0

Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

Can Debug Be Tamed?
By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

How to Connect Questa VIP to the Processor Verification Flow
By Codasip - 27 Feb, 2019 - Comments: 0

Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process. Read more here. » read more

Why Analog Designs Fail
By Brian Bailey - 14 Feb, 2019 - Comments: 2

The gap between analog and digital reliability is growing, and digital designs appear to be winning. Reports show that analog content causes the most test failures and contributes significantly more than digital to field returns. The causes aren't always obvious, though. Some of it is due to the maturity of analog design and verification. While great strides have been made in digital circuit... » read more

Low Power Apps: Shaping The Future Of Low Power Verification
By Mentor, a Siemens Business - 13 Feb, 2019 - Comments: 0

This paper describes how verification and design engineers can make use of UPF 3.0 information model-based HDL and Tcl APIs to write useful low-power apps. We present low-power apps that can be used to solve complex verification issues and provide case studies and examples to demonstrate usage. To read more, click here. » read more

Week in Review: Design, Low Power
By Susan Rambo - 08 Feb, 2019 - Comments: 0

The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

Designing Networking Chips
By Ed Sperling - 07 Feb, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data. One of those shifts involves software-defined networking, where the greatest complexity resides in the software. That also has a big impact on the entire design flow, from pre-silicon to post-silicon. htt... » read more

Automotive IC Design Demands Next-Generation High-Sigma Verification
By Jeff Dyck - 07 Feb, 2019 - Comments: 0

By Jeff Dyck High-sigma analysis is required for verifying replicated components, like memory blocks and standard cells, and for demonstrating mission-critical reliability for automotive and medical applications. It is not feasible to verify to high-sigma using brute-force Monte Carlo, as this requires 10s of millions of simulations to reach 5-sigma and billions in order to reach 6-sigma. S... » read more

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