Luminary Panel Sees Progress In EUV Pellicle Adoption As Critical For EUV

By Jan Willis - 21 Nov, 2024 - Comments: 0

A significant focus of the 2024 SPIE Photomask and EUV conference was on EUV lithography and high-numerical-aperture (high-NA) EUV lithography, offering the potential to drive resolution to new heights. These EUV solutions bring new challenges such as pellicles, mask inspection, and smaller and smaller minimum mask dimensions. Progress has been impressive, according to lithography luminary Dr. ... » read more

A Wrap-Up Of Photomask Japan 2024

By Ingo Bork - 23 May, 2024 - Comments: 0

This year, I had the opportunity to attend the 30th Symposium on Photomask and NGL Mask Technology, also called Photomask Japan 2024 (PMJ), in Yokohama, Japan, from April 16 to 18. This well-regarded symposium brings together engineers from all over the world to share ideas on photomasks, NGL masks and related technologies. It was great being back to an in-person conference after four years ... » read more

High-NA EUV Complicates EUV Photomask Future

By Jan Willis - 17 Nov, 2022 - Comments: 0

The eBeam Initiative’s 11th annual Luminaries survey in 2022 reported EUV fueling growth of the semiconductor photomask industry while a panel of experts cited a number of complications in moving to High-NA EUV during an event co-located with the SPIE Photomask Technology Conference in late September. Industry luminaries representing 44 companies from across the semiconductor ecosystem partic... » read more

Gearing Up For High-NA EUV

By Mark LaPedus - 21 Oct, 2021 - Comments: 2

The semiconductor industry is moving full speed ahead to develop high-NA EUV, but bringing up this next generation lithography system and the associated infrastructure remains a monumental and expensive task. ASML has been developing its high-numerical aperture (high-NA) EUV lithography line for some time. Basically, high-NA EUV scanners are the follow-on to today’s EUV lithography systems... » read more

Survey: 2020 eBeam Initiative Annual Survey Results

By eBeam Initiative - 21 Jul, 2021 - Comments: 0

Aki Fujimura, the CEO of D2S, Inc. presented "The eBeam Initiative's Annual Survey Results at Photomask" at Photomask Japan 2021 in April 2021. Survey says that COVID has a net neutral business impact on total mask revenues. By 2021, 24% positive vs 20% negative COVID-related business predictions. 74% agree actinic inspection for EUV HVM by 2023, and more results. Click here to read more. » read more

What’s Next In AI, Chips And Masks

By Mark LaPedus - 19 Nov, 2020 - Comments: 0

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to talk about AI and Moore’s Law, lithography, and photomask technologies. What follows are excerpts of that conversation. SE: In the eBeam Initiative’s recent Luminary Survey, the participants had some interesting observations about the outlook for the photomask market. What were those observations? Fujimur... » read more

Mask Making Issues With EUV

By Mark LaPedus - 17 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

EUV Mask Readiness Challenges

By Mark LaPedus - 21 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and photomask technologies with Emily Gallagher, principal member of the technical staff at Imec; Harry Levinson, principal at HJL Lithography; Chris Spence, vice president of advanced technology development at ASML; Banqiu Wu, senior director of process development at Applied Materials; and Aki Fujimura, chief ... » read more

EUV Pellicle, Uptime And Resist Issues Continue

By Mark LaPedus - 26 Sep, 2018 - Comments: 0

Extreme ultraviolet (EUV) lithography is moving closer to realization, but several problems involving scanner uptime, photoresists and pellicles need to be resolved before this long-overdue technology is put into full production. Intel, Samsung and TSMC are hoping to insert EUV into production at 7nm and/or 5nm. While the remaining issues don’t necessarily pre-empt using EUV, they do affec... » read more

Challenges Mount For Photomasks

By Mark LaPedus - 21 Sep, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss photomask technologies with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); Banqiu Wu, principal member of the technical staff and chief technology officer of the Mask and TSV Etch Division at [getentity id="22817" e_name="Applied Materials"]; Weston Sousa, general manager of the Reticle Products Division at [getentity id="22876" commen... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?