More Data, More Redundant Interconnects


The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Die-to-die Interconnect Standards In Flux


UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging


The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these app... » read more

Chip Complexity Drives Innovation In Automated Test Equipment


Innovations in semiconductor technology—such as advancements in AI high-performance computing (HPC), Angstrom-scale silicon process nodes, silicon photonics, and automotive xEV wideband gap power transistor applications—require automated test equipment (ATE) to evolve at an unprecedented rate. As chip complexity grows, the challenges in design, manufacturing, and test multiply. It is a comp... » read more

Three-Way Race To 3D-ICs


Intel Foundry, TSMC, and Samsung Foundry are scrambling to deliver all the foundational components of full 3D-ICs, which collectively will deliver orders of magnitude improvements in performance with minimal power sometime within the next few years. Much attention has been focused on process node advances, but a successful 3D-IC implementation is much more complex and comprehensive than just... » read more

TSMC Tech Symposium 2025


TSMC held its North America Technology Symposium on Wednesday, April 23, 2025 at the Santa Clara Convention Center and presented update information on its relentless march to ever finer geometries and higher levels of scaling. Figure 1, below, shows TSMC’s latest advanced technology roadmap. Compared to the roadmap presented at last year’s tech symposium, the new roadmap shows the “Hig... » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)


A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

Advanced Packaging Fundamentals for Semiconductor Engineers


Advanced packaging is inevitable. Large systems companies and processing vendors already are working with various types of highly engineered packaging. The rest of the semiconductor industry will follow at some point, whether they're designing their own packages, developing the tools, processes, materials, and methodologies to create them, or developing components that will be used inside of th... » read more

Nearly Invisible: Defect Detection Below 5nm


Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Need For KGD Drives Singulated Die Screening


The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly higher than with a single die. Better methods for inspecting and testing these devices are already starting to roll out. High-throughput infrared inspection is capable of catching more sub-surface d... » read more

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