tag: advanced packaging

Front-End Technologies Are The New Back-End Tools: Using Picosecond Ultrasonics Technology For AI Packages, Part 1
By Cheolkyu Kim - 10 Jun, 2025 - Comments: 0

If you are a part of the semiconductor industry or simply someone interested in the field, you have likely heard what has become a common refrain: the back-end of the process is becoming more like the front-end of the process. In other words, the technologies that were once exclusively deployed in the first part of the process are being used to meet the increasingly stringent requirements of ad... » read more

Big Changes In Medical Electronics
By Ed Sperling - 09 Jun, 2025 - Comments: 0

Medical devices are becoming more capable, more complicated, and more deployable in the field rather than in a hospital or a doctor's office. But getting these purpose-built devices into the hands of consumers requires a whole bunch of new challenges, from safeguarding fragile on-board chemistries that can be destroyed by existing chip manufacturing and packaging processes to ensuring the mater... » read more

Co-Packaged Optics Reaches Power Efficiency Tipping Point
By Laura Peters - 02 Jun, 2025 - Comments: 0

Commercialization has started for network switches based on co-packaged optics (CPO), which are capable of routing signals at terabits per second speeds, but manufacturing challenges remain regarding fiber-to-photonic IC alignment, thermal mitigation, and optical testing strategies. By moving the optical-to-electronic data conversion as close as possible to the GPU/ASIC switch in data center... » read more

Thermo-Mechanical Stress On Active Chiplets In A 3D-IC Heterogeneous Package Assembly
By Siemens EDA - 29 May, 2025 - Comments: 0

The move to heterogeneous multi-chip/chiplet products improves yield, performance and modularity while reducing power and overall product footprint. However, this shift to heterogeneous assembly also introduces new complexities that can influence chip warpage and circuit behavior due to thermo-mechanical stress impacts. In heterogeneous 3D IC architectures, the interaction between the chips ... » read more

More Data, More Redundant Interconnects
By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging
By Al Gamble - 08 May, 2025 - Comments: 0

The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these app... » read more

Chip Complexity Drives Innovation In Automated Test Equipment
By Jeorge Hurtarte - 08 May, 2025 - Comments: 0

Innovations in semiconductor technology—such as advancements in AI high-performance computing (HPC), Angstrom-scale silicon process nodes, silicon photonics, and automotive xEV wideband gap power transistor applications—require automated test equipment (ATE) to evolve at an unprecedented rate. As chip complexity grows, the challenges in design, manufacturing, and test multiply. It is a comp... » read more

Three-Way Race To 3D-ICs
By Ed Sperling - 05 May, 2025 - Comments: 1

Intel Foundry, TSMC, and Samsung Foundry are scrambling to deliver all the foundational components of full 3D-ICs, which collectively will deliver orders of magnitude improvements in performance with minimal power sometime within the next few years. Much attention has been focused on process node advances, but a successful 3D-IC implementation is much more complex and comprehensive than just... » read more

TSMC Tech Symposium 2025
By Barry Pangrle - 28 Apr, 2025 - Comments: 0

TSMC held its North America Technology Symposium on Wednesday, April 23, 2025 at the Santa Clara Convention Center and presented update information on its relentless march to ever finer geometries and higher levels of scaling. Figure 1, below, shows TSMC’s latest advanced technology roadmap. Compared to the roadmap presented at last year’s tech symposium, the new roadmap shows the “Hig... » read more

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