tag: advanced packaging

Globally Asynchronous, Locally Synchronous Clocks
By Ed Sperling - 04 Nov, 2024 - Comments: 0

Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to save energy, or they may age at different rates, which in turn reduces performance. Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes ... » read more

Advanced Packaging Driving New Collaboration Across Supply Chain
By Gregory Haley - 24 Oct, 2024 - Comments: 0

The semiconductor industry is undergoing a profound shift in packaging technologies to ones that rely on close collaboration among multiple stakeholders to solve intricate, multi-faceted, and extraordinarily complex problems. At the heart of this change is the convergence of heterogeneous integration, chiplets, and 3D stacking. Heterogeneous approaches allow companies to combine different te... » read more

Revolutionizing IC Packaging With High-Density RDL Technology
By Curtis Zwenger - 24 Oct, 2024 - Comments: 0

The demand for high-performance devices, particularly in AI, HPC, and data centers, has surged dramatically in the ever-evolving landscape of integrated circuit technology. This demand has been further accelerated by the COVID-19 pandemic, pushing the boundaries of silicon technology to its limits. Enter Amkor’s S-SWIFT, a packaging solution designed to address these challenges and revolution... » read more

Multi-Tier Die Stacking Enables Efficient Manufacturing
By Jessica Albright - 24 Oct, 2024 - Comments: 0

Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency without sacrificing device performance. Vertical integration techniques, such as multi-tier die stacking and hybrid bonding, enable increased integration density, therefore improving yield of high-quality devices. However, these highly precise processes require significant attention to defectivity... » read more

New Approaches To Power Decoupling
By Bryon Moyer - 24 Oct, 2024 - Comments: 0

Decoupling capacitors have long been an important aspect of maintaining a clean power source for integrated circuits, but with noise caused by rising clock frequencies, multiple power domains, and various types of advanced packaging, new approaches are needed. Power is a much more important factor than it used to be, especially in the era of AI. “Doing an AI search consumes 10X the power t... » read more

Monolithic Vs. Heterogeneous Integration
By Ed Sperling - 24 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss two very different paths forward for semiconductors and what's needed for each, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Po... » read more

Reactionary Or Anticipatory?
By Brian Bailey - 21 Oct, 2024 - Comments: 0

The EDA industry is located at an interesting place, where anticipation and reaction come together. Too much of either one is wasteful, but too little leaves the industry having to deal with unwanted problems. We see this happening in several areas today, and the balance is changing for several reasons. We normally expect universities to be 100% anticipatory. There is no point in them worki... » read more

3DIO IP For Multi-Die Integration
By Lakshmi Jain - 17 Oct, 2024 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity presents two significant challenges: manufacturability and cost. From a manufacturing standpoint, these processing engines are nearing the maximum size that lithogra... » read more

The Long Climb: Bringing Through Glass Vias (TGV) To High-Volume Manufacturing
By Keith Best - 15 Oct, 2024 - Comments: 0

The semiconductor industry is a land of peaks and valleys. It’s a place where each innovation represents the culmination of a long and often difficult climb to the summit. In the case of glass substrates, the peak of the mountain is in sight. The arrival of glass substrates comes at an opportune time, as the industry eyes new process innovations to meet the incredible demand for high perfo... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs
By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

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