tag: advanced packaging

New Design Approaches At 7/5nm
By Ed Sperling - 04 Mar, 2019 - Comments: 0

The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

In-Memory Vs. Near-Memory Computing
By Mark LaPedus - 21 Feb, 2019 - Comments: 1

New memory-centric chip technologies are emerging that promise to solve the bandwidth bottleneck issues in today’s systems. The idea behind these technologies is to bring the memory closer to the processing tasks to speed up the system. This concept isn’t new and the previous versions of the technology fell short. Moreover, it’s unclear if the new approaches will live up to their billi... » read more

Unsticking Moore’s Law
By Ed Sperling - 04 Feb, 2019 - Comments: 2

Sanjay Natarajan, corporate vice president at Applied Materials with responsibility for transistor, interconnect and memory solutions, sat down with Semiconductor Engineering to talk about variation, Moore's Law, the impact of new materials such as cobalt, and different memory architectures and approaches. What follows are excerpts of that conversation. SE: Reliability is becoming more of an... » read more

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Low Power At The Edge
By Ed Sperling - 17 Jan, 2019 - Comments: 0

The tech world has come to the realization in recent months that there is far too much data to process everything in the cloud. Now it is starting to come to grips with what that really means for edge and near-edge computing. There still are no rules for where or how that data will be parsed, but there is a growing recognition that some level of pre-processing will be necessary, and that in tur... » read more

More 2.5D/3D, Fan-Out Packages Ahead
By Mark LaPedus - 15 Jan, 2019 - Comments: 0

A new wave of 2.5D/3D, fan-out and other advanced IC packages is expected to flood the market over the next year. The new packages are targeted to address many of the same and challenging applications in the market, such as multi-die integration, memory bandwidth issues and even chip scaling. But the new, advanced IC packages face some technical challenges. And cost remains an issue as advan... » read more

Reducing Advanced Packaging Costs
By Ed Sperling - 09 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

EDA, IP Show Strong Growth
By Ed Sperling - 07 Jan, 2019 - Comments: 0

EDA and IP revenue increased 6.7% worldwide in Q3 2018 to $2.44 billion, compared to $2.28 billion in the same period in 2017. The growth was fueled by rising investments in startups in AI and 5G, as well as a stampede of new and existing companies targeting automotive electrification and autonomous vehicles. While startup funding ultimately will run out as these new markets mature and cons... » read more

Top Stories from 2018
By SE Staff - 03 Jan, 2019 - Comments: 0

After years of consolidation, the semiconductor industry in 2018 underwent an interesting time of transition and uncertainty. From concerns about scaling limits, aging chips and new architectures, here are most-read stories of 2018. [gallery columns="1" size="full" ids="24134285,24135205,24142311,24137395,24131667,24137111,24131651,24140136,24131128,24133163,24138972,24139330"] » read more

What’s the Right Path For Scaling?
By Mark LaPedus - 02 Jan, 2019 - Comments: 1

The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to take a harder look at different options for future devices. Scaling is still on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some option... » read more

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