EDA Grabs Bigger Slice Of Chip Market

Manufacturing, packaging and development tools always have earned a fixed percentage of IC revenue, but that could change.

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EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019.

With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle the pressures that artificial intelligence, automation and security put on systems. But how long will this sweet spot last for EDA?

EDA revenue consistently has been 2% of semiconductor revenue, as Wally Rhines, CEO Emeritus for Mentor, a Siemens Business, has said on the record many times. Now he sees a growing pie for EDA. “Revenue growth for EDA continues to be remarkably strong, powered by new entrants into the IC design world, such as Google, Facebook, Amazon, Alibaba, etc., along with automotive system and Tier1 companies, as well as an abundance of new AI-driven fabless semiconductor start-ups,” says Rhines. “Since design activity precedes semiconductor revenue growth, we can expect strong EDA company performance in 2019.”

In addition, several of those new entrants are not looking to make money from the silicon itself, but from the services enabled by the silicon. Design speculation is picking up, and all of those design starts need tools even if they don’t result in profitable silicon. Alongside of that, venture capital is beginning to flow into the design world.

This suggests a short-term increase for EDA revenues in percentage terms. “The ASIC is back,” proclaims Chi-Ping Hsu, executive advisor at Avatar Integrated Systems. “With more IPs available and more EDA automation, there will be new vertically integrated, automated platform solutions to reduce ASIC design efforts and costs. Large mega ASSP companies, in addition to high-volume ASSPs, will aggressively engage in ASIC design to leverage their IPs and domain knowledge. At the same time, many independent and foundry-affiliated design service companies will thrive with the new wave of system customers who want to differentiate through their own ASICs in the systems.”

The makeup of those chips may be slightly different from the past. “We will see an increased use of ASIC platforms with open source cores and languages and embedded FPGAs to address the need of customizability as well as reprogrammability,” says Ranjit Adhikary, vice president of marketing for ClioSoft. “Applications such as AI, autonomous driving and industrial automation, when implemented on the edge, require high performance with low latency and low power usage to respond to real-time changes in conditions. The ability to learn, assess and adapt to continuously changing scenarios will require the ability to reprogram and will assist in keeping the product cost down.”

The industry has a new component to help provide sufficient programmability. “Embedded FPGA will enter the mainstream,” says Geoff Tate, CEO for Flex Logix. “More major companies will announce the licensing and use of eFPGA in a wide range of chips from wireless to aerospace to networking. eFPGA will continue to steadily increase in availability across process nodes and foundries.”

Adhikary agrees. “Solutions using embedded FPGAs address the problem of inflexibility in ASICs by enabling new products to achieve a balance between performance and reprogrammability and yet deliver the performance that real-world machine-learning systems require.”

Some of this comes about because of new market segments. “A few years ago, system-on-chip (SoC) architectures were focused on smart phone and tablets,” says Sergio Marchese, technical marketing manager at OneSpin Solutions. “Today’s leading-edge AI-centric designs include embedded FPGA fabric as well as software-programmable processing engines. We expect several families of such devices.”


Fig. 1: Growth by segment. Source: ESD Alliance MSS

Manufacturing changes
This uptick in design starts may not follow the traditional path of utilizing the latest process nodes. “If smartphone unit sales continue to decline, the number of advanced wafers consumed will be reduced,” says Tom Wong, director of marketing, design IP at Cadence. “While this may lead to more 7nm wafers being available to other customers, very few applications can consume the equivalent wafer demand of 50 million chips a year. This phenomenon may slow the need for a quick transition to 5nm, as there will be ample capacity at 7nm for everybody.”

In addition, extra fab capacity is available from the plunge in cryptocurrencies. (See related story, Mostly Upbeat Outlook For Chips.)

New packaging technologies are beginning to look a lot more attractive, as well. “The interesting development is that while everyone continued to go down the familiar road and enhance process technology, they have gotten to the point where that is not so easy anymore,” says Thomas Uhrmann, director of business development at EV Group. “Now we see different paths into the future. It is no longer just about the chip level. The major benefits that we will see are in the system level. The whole supply chain is optimizing itself to lower cost to make it mainstream.”

While most of the advanced packaging so far has been in fan-outs, system-in-package and 2.5D, full 3D integration is starting. “3D-IC and other sophisticated packaging technologies will take off,” says Wilbur Luo, Cadence. “Costs have come down and research has ramped up on innovative packaging technologies. Virtually every combination of stacking (side-by-side, vertical, both) will be utilized.”

This will have a significant impact on design flows. “The explosion of options for assembling and packaging semiconductors being offered by IC foundries and OSATs will require system architects to do more up-front design exploration and tradeoffs before committing to final architectures for chips and packages,” says John Park, product management director for IC packaging and cross-platform solutions at Cadence. “System architects will turn to EDA tools to help them more easily explore physical, electrical and thermal design options and variants at the system level.”

New classes of tools may be required, as well. “Structural electronics, also referred to as 3D electronics, is the integration of circuitry and discrete electronic components into 3D structures,” explains Dan Fernsebner, product marketing group director for PCB and IC packaging at Cadence. “Extending electronics into the 3D space provides a new dimension of design, simplifying the electrical and mechanical assembly and providing higher reliability due to less susceptibility to moisture, vibration and temperature variances. These advantages are driving the industry need to adopt structural electronics, but it is being counteracted by the lack of CAD software to support electrical three-dimensional design. Design capability enhancements will require a full 3D electrical design environment with the ability to route and place components on any surface or on the interior of a 3D structure, enhanced manufacturing outputs to understand three-dimensional manufacturing, and new design rule checks.”

Packaging needs to become more formalized. “When designing an IC, it’s almost unheard of to begin the process without a reference flow and process design kit,” says Park. “However, package designers tape out thousands of designs every year without either. For the IC foundries that are expanding their offerings to include advanced packaging technologies. Providing their customers with reference flows and PDKs is a natural progression. This puts pressure on the OSATs, who are now offering more sophisticated packaging solutions to provide their customers with the same level of reference material. This will greatly benefit the semiconductor packaging community.”

The bottom line, according to Park, “is that semiconductor packaging will experience a major inflection point with 3D IC. Expect to see the beginnings of this in 2019.”

This does not mean the foundries are standing still on process technologies, however. “The foundries are revamping some of the older technologies for better performance,” says Navraj Nandra, senior director of product marketing for the Solutions Group at Synopsys. “40nm has been around for 10 years, but that process today looks very different because they have added ultra-low power devices with very thick gate oxides, they have added embedded flash technology. This changes the SPICE models, it changes the transistor behaviors, and the IP that was developed 10 years ago needs to be refreshed.”

It will make for a turbulent period. “Semiconductor and adjacent industries will continue to experience unprecedented consolidation in 2019, changing supply chain dynamics and opening doors to new players as the industry moves from monolithic to wide-ranging devices, bringing innovation unheard of five years ago,” says Bob Smith, executive director for ESD Alliance, a SEMI Strategic Association Partner. “This innovation is not possible without the system design ecosystem, now firmly establishing itself as an important contributor to the semiconductor flow through efforts of global industry associations.”

IP impact
New markets, packaging and business factors are pressuring the IP industry to change. “In 2019, RISC-V will cross the commercial chasm with many practical semiconductor projects adopting the open instruction set,” says Dave Kelf, CMO for Breker Verification Systems. “This will be the most disruptive force the industry will have experienced in many years. Processor IP companies will not be able to react effectively as the extended instruction set processor market will be overwhelmed. Numerous tools, design flows and IP will be announced from many sources—except the big companies, which will be notably absent as they try and figure out their strategies.”

Open-source hardware and software could have a big impact on the IP world. “We have been following the rapid evolution of the RISC-V ecosystem and believe that 2019 will be year that it explodes,” says OneSpin’s Marchese. “A surprising number of companies are doing their own processor designs, but there will clearly be some strong IP options for those who want to buy rather than build. The ecosystem will offer many opportunities for tools and services to verify this new and novel instruction-set architecture (ISA), including the use of formal technologies.”

RISC-V is not standing still. “There are new features that are complete enough that trial implementation will start in 2019,” says Krste Asanovic, professor at UC Berkeley and chief architect for SiFive. “This includes vector extensions, the hypervisor, and we are also working on DSP extensions. They are being defined now and over the course of the next year they will be implemented and potentially ratified.”

Work still needs to be done on the ecosystem, but progress is rapid. “A lot of money is coming into RISC-V. A lot of people want to have higher performance processors and the software community is excited to make that happen,” adds Asanovic.

The change in market drivers also is impacting connectivity IP. “There will be new cache coherency requirements, CCIX, and a lot more focus on the latency of these interfaces especially when you add storage elements,” says Nandra. “There will be more PCI Express Gen5 implemented in high-end ML chips, and I speculate that LPDDR5 will find automotive to be the key driver. You will see more 3D or 2.5D type packaging. People are stacking DRAM using TSVs to increase capacity for DDR, and that will continue. You will see multiple stacked HBM2 memories. There are a lot more displays in cars—both heads up and mirrors that are being replaced. That puts new requirements into displays. MIPI PHY controller IP is important for this.”

And with more IP and a wider range of requirements, keeping track of everything becomes more important. “Design companies will seek to better leverage their internal IPs in their designs, track their usage and better protect them,” adds Adhikary. “They will look for IP management solutions which can manage a complex matrix of information regarding the IP such as foundry, process node, PDK version, revision, silicon proven, design views available, and is not tied to any data management solutions.”

Impact on tools and flows
With so many changes in the ecosystem, the requirements for tools are evolving. “What is both exciting and challenging for EDA is developing the cutting-edge solutions needed to address emerging semiconductor design technology demands,” says Rhines. “These include new compute architectures, the emergence of photonics, an increase in lithographic complexities involving EUV and other techniques, more complex packaging, and a massive increase in data.”

Rhines also notes the continued merging of domains. “Embedded software, mechanical, PCB, packaging, electrical interconnect, networking (access to the intranet) and security are just a few of the domains that need to work closer together in a more integrated manner. The increasing complexity is also making each of the domains more demanding, pushing new materials and methodologies into the respective domains.”

Many of these changes impact verification. “New chips targeting artificial intelligence, deep learning and machine learning, 5G wireless applications, and RISC-V will be met with news from semiconductor design verification companies responding with new tools, technologies and methodologies,” says Michiel Ligthart, president and COO for Verific Design Automation.

Formal has been making strides in recent years. “FPGA formal equivalence checking from RTL to programming bitstream will become an absolute necessity,” says Marchese. “FPGA vendors continue to develop more aggressive optimizations to meet demanding power, performance and area (PPA) goals. Sequential equivalence checking is required to verify these design transformations. The growing importance of silicon trust will also be a driver in the use of equivalence checking to ensure that no Trojans have been introduced.”

2018 was a big year for Portable Stimulus (PS). “While there will be no revision to the standard in 2019, there will be a groundswell of new requirements as companies gain usage experience,” says Kelf. “Expect to see apps and libraries springing up for many purposes, both standard design flows and more advanced applications such as security and safety.”

Adoption will continue. “The ability of PS to describe complex system behaviors enables a shift-left for testing of system-level use cases without needing a complete production software stack,” points out Larry Melling, director for product management and marketing at Cadence. “PS will enable new methodologies extending UVM by simplifying the testbench, enabling portability of transaction-based verification across simulation, emulation and prototyping, and providing a smooth transition from coreless to core-based testing.”

But it is perhaps safety and security that force most changes to the verification flow. “Tools have the potential to play a much bigger role in preventing and controlling security attacks,” says Marchese. “In 2019, we expect to see numerous startups and some established industry players taking up this challenge. Security will grow in importance and progress toward achieving an equal footing with safety.”

Moving tools into the cloud was a big push for 2018. “More small and medium-sized companies will start using the cloud for designing their ASICs instead of investing in their own IT infrastructure,” says Adhikary. “Instead of using the cloud services offered by EDA companies, where they are stuck with using flows from only one company, they will formulate their own solutions where they can use best-in-class tools. There will be growth in software-defined data management infrastructure solutions which aid in the seamless and efficient management of dynamic, cloud-integrated workflows. These solutions will provide the necessary architectures to expand and accelerate the IT infrastructure, by facilitating efficient data access in the cloud and across hybrid cloud boundaries.”

2019 will require flexibility across the entire ecosystem. “The new year promises to be a challenging but rewarding time for the semiconductor industry,” says Rhines. “Domain-specific processors for AI and machine learning hold great promise but will require new EDA capabilities and solutions. We look forward to partnering with semiconductor designers to make 2019 a successful year for all.”

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