tag: advanced packaging

Photonics Moves Closer To Chip
By Ed Sperling - 20 Jun, 2016 - Comments: 0

Silicon photonics is resurfacing after more than a decade in the shadows, driven by demands to move larger quantities of data faster, using extremely low power and with minimal heat. Until recently, much of the attention in photonics focused on moving data between servers and storage. Now there is growing interest at the PCB level and in heterogeneous multi-chip packages. Government, academi... » read more

One-On-One: Dave Hemker
By Ed Sperling - 19 May, 2016 - Comments: 0

Dave Hemker, CTO at [getentity id="22820" comment="Lam Research"], sat down with Semiconductor Engineering to look at some of the key issues on the process and manufacturing side, and some of the key developments that will reshape the semiconductor industry in the future. What follows are excerpts of that conversation. SE: One of the big discussion topics these days is [getkc id="208" commen... » read more

The Evolving Thermal Landscape
By Ann Mutschler - 16 May, 2016 - Comments: 0

Managing heat in chips is becoming a precision balancing act at advanced nodes and with advanced packaging. While it's important to ensure that temperatures don't rise high enough to cause reliability problems, adding too much circuitry to control heat can reduce performance and lower energy efficiency. The most common approach to dealing with these issues is thermal simulation, which requir... » read more

No More Straight Lines
By Ed Sperling - 12 May, 2016 - Comments: 0

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

Power-Centric Chip Architectures
By Ed Sperling - 12 May, 2016 - Comments: 0

As traditional scaling runs out of steam, new chip architectures are emerging with power as the starting point. While this trend has been unfolding for some time, it is getting an extra boost and sense of urgency as design teams weigh a growing number of design challenges and options across a variety of new markets. Among the options are [getkc id="196" kc_name="multi-patterning"] and [getkc... » read more

Keeping The Whole Package Cool
By Katherine Derbyshire - 12 May, 2016 - Comments: 0

Heat dissipation is a critical issue for designers of complex chip-stacking and system-in-package devices. The amount of heat generated by a device increases as the number of transistors goes up, but the ability to dissipate the heat depends on the package surface area. Because the goal of 3D packaging is to squeeze more transistors into less overall space, new heat dissipation issues are em... » read more

2.5D Becomes A Reality
By Ed Sperling - 11 May, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

2.5D Becomes A Reality
By Ed Sperling - 27 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Rightsizing Challenges Grow
By Ed Sperling - 20 Apr, 2016 - Comments: 0

Rightsizing chip architectures is getting much more complicated. There are more options to choose from, more potential bottlenecks, and many more choices about what process to use at what process node and for which markets and price points. Rightsizing is a way of targeting chips to specific application needs, supplying sufficient performance while minimizing power and cost. It has been a to... » read more

EDAC Changes Name
By Ed Sperling - 31 Mar, 2016 - Comments: 1

The EDA Consortium today changed its name to the Electronic System Design Alliance, a move that expands the group's charter to reflect shifts that have been underway in the chip design world for some time. Those shifts include the growth in IP and an increased focus on software development. Classic EDA, from place and route to synthesis to back-end debug and verification, are still very much... » read more

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