One-On-One: Dave Hemker

Dave Hemker, CTO at Lam Research, sat down with Semiconductor Engineering to look at some of the key issues on the process and manufacturing side, and some of the key developments that will reshape the semiconductor industry in the future. What follows are excerpts of that conversation.

SE: One of the big discussion topics these days is . How far can we go with 3D NAND? How many layers can we have?

Hemker: We’re at 32 layers now. People are talking about going to 48. In the labs, they’re looking at 60-plus or 90-plus. What’s fun about being at this stage is we don’t know, and the answer always is more surprising than you would expect. You do something and you think it’s amazing, and five years later you’re still doing it and improving it.

SE: But 3D NAND has legs for years to come, right?

Hemker: Yes. The way I look at it, from an equipment point of view, is that you have knobs you can play with. The number of layers is the obvious one, but there also is the thickness of the layers and the actual pitch of each of the cells. There is also talk about taking whatever number of layers you’re comfortable making and stacking them. So you do it once, then repeat it. That raises questions about how you’re going to do overlay. It’s complicated, like everything else. There are ways you can play around with the storage device itself in terms of being able to get better retention and multi-level cells. The scaling on that has room. We’re just at the very beginning. It’s not a one- or two-generation thing.

SE: What happens on the equipment side?

Hemker: 3D NAND is enabled by dep (deposition) and etch. If you’re a device maker and things get more complicated and expensive at every node, you have to make decisions about what path you’re going to pursue. On the planar flash side, the decision was made for them by physics. They couldn’t hold the electrons anymore or distinguish if it’s a one or a zero, especially if it’s multi-level. So everyone realized they had to do something different. With planar, the litho was at the limit to pack everything in tightly to make the capacitors. With 3D, the nominal lithography is about 40nm litho. You’re not at 7nm or 1x, 1y or 1z litho anymore. But then it added to dep and etch intensity. The transistor is no longer defined by an etch feature. It’s defined by a dep thickness. The repeatability of that stack is critical to get a device that’s usable.

SE: 3D NAND typically is associated with data centers. Will it branch out?

Hemker: In data centers it’s more expensive than spinning hard drives. But when you look at the power consumption, the density and the scalability, it starts to look very attractive. It will hit 100% saturation in laptops. Even if you’re working on a desktop PC, your boot drive is going to be SSD and you will have a spinning drive to store things. The whole memory space is interesting. There are potential future inflections in memory, as well. If you look at 3D-XPoint from Micron and Intel, it’s an indication of the way things can go in the future. In the past there was just memory. Then NAND came in and you had DRAM and NAND. There was volatile and non-volatile and each had their distinct uses. It was simple to differentiate because they’re far apart in terms of density, cost and durability. Now you have a memory that is non-volatile, denser than DRAM but faster than traditional NAND, and cost-competitive. It fits right in this memory continuum, which they’ve dubbed storage-class memory. If it were as fast as DRAM and as inexpensive, it would be the universal memory. We’ll keep aiming for that.

SE: There seems to be a lot of development in the memory side these days.

Hemker: Yes, and I don’t see any slowing in demand for memory. But it will become more specialized, which will drive a lot of the new work we’re doing. If you look at the number of levels of cache, and high-bandwidth memory, Hybrid Memory Cube, specialization is going to be important. Twenty years ago, and to some extent today, you had a general-purpose processor. Now I want every transistor on my smart phone doing something useful for my application, rather than a capability I’m not using that I need to power down. That’s another example of fragmentation in the logic space.

SE: How about advanced packaging? Where you see this going?

Hemker: We’re active in the drilling of holes for TSVs. We’ve got etch and fill—electroplating for packaging.

SE: One of the problems with drilling was that it was stressing the silicon, right?

Hemker: Yes, and it’s getting easier as we thin down die. There is less substrate to go through.

SE: That seems counterintuitive. You would think it would be more difficult if the substrate is thinner.

Hemker: Yes, but the layouts now are much more aware of that. Where you place the vias is not just important from the device standpoint, but also from the stress and thermal management standpoint, as well. It’s definitely gotten more mature. The big question there is what applications need it. At one point, people were saying everything needs it, which isn’t the case. Some image sensors need it. Mobile needs it from a form-factor sense. And the other place is where it adds to performance, which is the high-bandwidth memory or the Hybrid Memory Cube architectures where you really need to improve the data flow between the processor and memory. And they’re willing to pay for it because it does add cost.

SE: How about lithography. How do you see it evolving?

Hemker: Patterning is still going to be important. When EUV comes in, it likely will still be in the hybrid mode. It probably won’t happen before 7nm. It’s not going to be something where you wake up and the world is different because EUV is in production. It’s going to be gradual. Someone will get a stepper. Maybe they will try it in parallel to compare yields. It will probably get serious at 5nm. But even then, a lot of it is going to be complementary. Multiple patterning isn’t going away because a lot of the equipment is depreciated now. Yields are up, defect levels are down. The industry has gotten pretty good at it. The future will be mix and match. If everyone is at 1D layouts, that’s great for classic multiple patterning. Maybe you do an EUV and you double pattern it. There is talk about complementary e-beam, but if EUV works that’s work it will go right away.

SE: But isn’t one of the fundamental changes that we’re not just doing one thing anymore? There are lots of things that need to be done at each new node.

Hemker: Yes, and that’s how we extended . Is there room for optimization? Yes. Every chip on the leading edge now uses multiple patterning because we’ve gotten good at it. But the actual process of optimization is this very interconnected set of tools and processes and integration flows.

SE: Where do we start running into problems that become intractable? Are we good into the Angstrom world?

Hemker: When you push beyond 3nm, we’re into the Angstrom world. From my perspective, we’re living on this exponential curve of Moore’s Law. It has always been this steep when you’re on it. But in order to solve it, we are having to turn more knobs simultaneously. If you look at logic transistors, there’s a good road map. It’s seven years out, and Intel always has the road ending in a fog bank. Still, just because you can’t see it doesn’t mean it ends. Predicting the end of Moore’s Law is like predicting a bear market. Eventually you’re going to be right. I’ve talked about the broadening of Moore’s Law. You see one node hanging on longer. So when you look at each section of where we have to make advances, you can slice up the fin on a finFET so it becomes a gate-all-around nanowire. There are then options to go to vertical nanowires. The 3D NAND development is an interesting one because it’s a kind of pathfinder for us. There may be options where you keep doing what you’re doing, but you then stack. Maybe solving that problem isn’t quite as difficult as the other ones. Technically, there is at least another 10 years. From an economic standpoint, that’s a whole other thing that’s obviously very important.

SE: But it doesn’t necessarily roll out every two years, right?

Hemker: Correct, and that comes from end demand, too. If someone takes three years to develop something and they have an advantage with the chip they’re making, that will pull it along.

SE: So what do people actually want and need? Is it the processor speed or is it what you’re trying to accomplish?

Hemker: I don’t lose sleep over the need for more computing power or the need for more memory storage. If you look at what’s going on with machine learning, why shouldn’t that be in my pocket in 10 years? I want to be able to pull it out and have a natural language interface. We’ll be looking at Watson on Jeopardy in the future and people will be holding up a small device and saying, ‘This has twice as much as that.’ Whether that’s in 10 years or 20 years we don’t know. You can see this with speech recognition, though. Early on, they were trying to be clever with algorithms as opposed to having every word and waveform stored in something and you can use a simple lookup table. We’re on that cusp as well with Alexa Voice from Amazon and Siri. There is still a lot of room for improvement, but this is a big change.

SE: How about equipment? Does it extend from one node to the next, or do you have to change it all out?

Hemker: Customers never want to change equipment unless they absolutely have to. So then the question becomes, how many ‘absolutely have to’s’ do you have to have at each node. It can vary. Aluminum to copper was a huge one. When you look at planar to 3D NAND, the amount of reuse is less than planar to planar. But our customers have optimized how to do reuse, so if there is a way to make existing stuff work, they will.

SE: Don’t 2.5D and 3D stacking play into that, as well?

Hemker: Yes. If you’re an OSAT you probably don’t have TSV capability, but there’s a subset you need when you jump to that. You need to make a new investment. On the equipment side we have to come up with new capability every node. As an equipment vendor, what we have to do is make it retrofittable or an upgrade, so you don’t have to throw the whole thing away. It may be part of the chamber or the plasma source technology in terms of etch. The process control angle will help us going forward, as well. If we can move process control more tightly into the processing as we’re designing equipment, so we design with process control in mind, that will give us some extra ability to scale, as well.

SE: How far can finFETs be extended?

Hemker: There will be two or three or more finFET nodes, and it will really be a question of whether you’re changing the material, or whether you go to horizontal nanowire? The transistor hasn’t changed, but can you get the I^on/I^off with the feature size that you need. The problem is that the fins are smaller than the actual node. It’s hard to predict whether it’s an extra node or not, but the question is how does it look with some germanium coming in. What does that buy you? We’re working on horizontal nanowires right now, and there are some interesting things you can do once you start introducing germanium in terms of being able to selectively remove silicon relative to germanium, or the inverse of that, as well.

SE: What’s the tradeoff there?

Hemker: It will probably be an alloy of silicon and germanium. That will come from your transistor performance requirements. Because we can get the selectivity, if you’re going to make alternating layers of germanium-rich and silicon-rich and you can selectively etch those out, then suddenly you have things that look like horizontal nanowires. So now you can do a gate all around and you get much better electrostatics. It’s much more complicated than what we’re doing now, but it’s a natural progression of the finFET. We’re doing work with some universities on vertical nanowires, too, which are great if you can actually make them and make contacts to them. Now you’ve decoupled transistor performance from the density. You have to shrink them down and make them smaller and smaller, so leakage goes up every generation. This way the leakage is dependent on how tall is the wire, and the packing density is the diameter. So now they’re more independent. You still have to etch these things and fabricate them and there’s a lot of work that has to be done.

SE: This used to be the realm of quantum physics, right?

Hemker: Yes, and you’re getting quantum effects here. There are things that are three atoms wide. That’s the challenge for us from an etch perspective and dep. All of the feature sizes now are on the order of nanometers. The variation is on the order of Angstroms because you have a 10 Angstrom window. Our critical feature control has to be under 0.5nm. That’s 5 Angstroms. A bond length is 2.5 Angstroms. We’re doing atomic-level engineering. That’s one of the new tools we’ll need. You need to peel off one layer in such a way that you have a perfect etch front, the same way you will need perfect conformality.

SE: How do you measure that?

Hemker: There are two different sides to that. One is when you’re doing development. There you need high-resolution TEMs (transmission electron microscopes), and there you’re going to need atomic-force microscopes. You can get some atomic-level resolution and see whether the lattice is still intact. What you do in production is different. Hopefully you design a big enough process window so that you don’t have to be doing TEMs.

SE: Isn’t that the tradeoff, namely how we get enough throughput and still manage to have that kind of control?

Hemker: Yes. The good thing is that from an etch and dep perspective, as things are getting smaller they’re also getting thinner. There are lots of circumstances now where you can look at how much ALD is used in multi-patterning. Because you’re putting less material down, you don’t have to add half a micron. You can do 10nm in a very reasonable time frame, so ALD and ALE become very economical.

SE: So just to be clear, when exactly do quantum effects begin entering the picture?

Hemker: There already are tunneling effects, and there are devices we’re looking at that will take advantage of that. So you have MRAM magnetic tunneling junction stacks where you can take advantage of the quantum tunneling to interrogate whether that’s a one or a zero. Some people are looking at that to be a transistor—a spin valve gate. We’re trying to take advantage of that and engineer it in. But there are a lot of materials that are needed to make sure that effect is reliable and controllable. Every time you have multiple materials, you have interfaces. If you look at how thin these materials are, it’s all interfaces. There is no bulk anymore. This is interface management. In our research programs, we’re looking at how to engineer those interfaces in ways that you want. With some of these you’re not even worrying about electrons. You’re using a magnetic effect—the spin of the atoms.

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