tag: advanced packaging

Intel Vs. Samsung Vs. TSMC
By Ed Sperling - 15 Jul, 2024 - Comments: 3

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs. Unlike in the past, when a single industry roadmap dictated how to get to the next... » read more

X-ray Inspection Becoming Essential In Advanced Packaging
By Gregory Haley - 09 Jul, 2024 - Comments: 0

X-ray technology is moving into the mainstream of chip manufacturing as complex assemblies and advanced packaging make it increasingly difficult to ensure these devices will work as expected throughout their lifecycles. A single defect in a chiplet or interconnect can transform a complex advanced package into expensive scrap, and the risk only increases as the chip industry shifts from homog... » read more

U.S. Proposes Restrictions On Tech Investments In China
By Linda Christensen - 24 Jun, 2024 - Comments: 1

The U.S. proposed new regulations to curtail American investments in Chinese technologies that pose a national security threat, specifically calling out semiconductors and microelectronics, quantum information technologies, and AI. The draft regulations come nearly a year after the Biden administration issued an executive order prohibiting investments in sensitive technologies used to accele... » read more

Controlling Warpage In Advanced Packages
By Laura Peters - 24 Jun, 2024 - Comments: 1

Warpage is becoming a serious concern in advanced packaging, where a heterogeneous mix of materials can cause uneven stress points during assembly and packaging, and under real workloads in the field. Warpage plays a critical role in determining whether an advanced package can be assembled successfully and meet long-term reliability targets. New advances, such as molding compounds with impro... » read more

Power-Aware Revolution In Automated Test For ICs
By Gregory Haley - 11 Jun, 2024 - Comments: 0

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip. Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously consider... » read more

Comparing Thermal Properties In Molybdenum Substrate To Si And Glass For A System-On-Foil Integration (RIT, Lux)
By Technical Paper Link - 31 May, 2024 - Comments: 0

A technical paper titled “Comparative Analysis of Thermal Properties in Molybdenum Substrate to Silicon and Glass for a System-on-Foil Integration” was published by researchers at Rochester Institute of Technology and Lux Semiconductors. Abstract: "Advanced electronics technology is moving towards smaller footprints and higher computational power. In order to achieve this, advanced packag... » read more

Package Assembly Design Kits: The Future Of Advanced Package Design
By Ruben Fuentes - 23 May, 2024 - Comments: 0

Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized heterogeneous design experience that optimizes the device's intended package performance with complete connectivity verification, DRC, and assembly validation. Another primary reason is the ongoing f... » read more

Adapting To Evolving IC Requirements
By Ed Sperling - 07 May, 2024 - Comments: 0

As chip designs become increasingly heterogeneous and domain-specific, packing a device with one-size-fits-all chips or chiplets doesn't make sense. The key is rightsizing different components based on real workloads, so they don't waste power when there is too little utilization of logic, and so they don't struggle to complete tasks because they are undersized. Jayson Bethurem, vice president ... » read more

Overlay Optimization In Advanced IC Substrates
By Ed Sperling - 29 Apr, 2024 - Comments: 1

Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are bak... » read more

Reduce 3D-IC Design Complexity: Early Package Assembly Verification
By Siemens EDA - 24 Apr, 2024 - Comments: 0

Uncover the unique challenges, along with the latest Calibre verification solutions, for 3D-IC design in this new technical paper. As 2.5D and 3D-ICs redefine the possibilities of semiconductor design, discover how Siemens is leading the way in verifying complex multi-dimensional systems, while shifting verification left to do so earlier in the design process. What you'll learn: Overcom... » read more

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