Chasing Test Escapes In IC Manufacturing


The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

A Novel Memory Test System With An Electromagnet For STT-MRAM Testing


We have successfully developed, for the first time, a new memory test system for STT-MRAM at wafer-level where an electromagnet is combined with a memory test system and a 300 mm wafer prober. In the developed memory test system, an out-of-plane magnetic field up to ±800 mT can be applied on 10 x 10 mm2 in the 300 mm wafer with distribution of less than 2.5%. We demonstrated that the electroma... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs IBM has unveiled what the company says is the world’s first 2nm chip. The device is based on a next-generation transistor architecture called a nanosheet FET. The nanosheet FET is an evolutionary step from finFETs, which is today’s state-of-the-art transistor technology. Targeted for 2024, IBM’s 2nm chip features a novel multi-Vt scheme, a 12nm gate length, and a n... » read more

Developers Turn To Analog For Neural Nets


Machine-learning (ML) solutions are proliferating across a wide variety of industries, but the overwhelming majority of the commercial implementations still rely on digital logic for their solution. With the exception of in-memory computing, analog solutions mostly have been restricted to universities and attempts at neuromorphic computing. However, that’s starting to change. “Everyon... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Intel wants $9.7 billion in subsidies for use in building a leading-edge fab in Europe, according to a report from Reuters. As reported, in March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Eighteen members of the European Union recently launched an ... » read more

Week In Review: Manufacturing, Test


Government policy At one point, there was a school of thought that the Biden administration would relax the current tariffs and export controls in regards to China. So far, the Biden administration hasn’t changed any of the previous policies and is doubling down on those efforts. The Department of Commerce’s Bureau of Industry and Security (BIS) this week added seven Chinese supercomput... » read more

AI In Inspection, Metrology, And Test


AI/ML is creeping into multiple processes within the fab and packaging houses, although not necessarily for the purpose it was originally intended. The chip industry is just beginning to learn where AI makes sense and where it doesn't. In general, AI works best as a tool in the hands of someone with deep domain expertise. AI can do certain things well, particularly when it comes to pattern m... » read more

Sharing Secure Chip Data For Analytics


New approaches and standards are being developed to securely share manufacturing and test data across the supply chain, moves that have long been considered critical to the reliability of end devices and faster time to yield and profitability. It will take time before these methods become widespread in the IC supply chain. But there is increasing agreement these kinds of measures are essenti... » read more

ATE In The Age Of Convergence And Exascale Computing


We are currently in the midst of the age of convergence – that is, the convergence of data from a range of applications and data sources. These sources constitute anything that creates data – ranging from human-created data, such as voice and video, through automotive, mobile, and wireless/IoT devices. This also includes edge computing and servers storing the massive amounts of data needed ... » read more

What Goes Wrong In Advanced Packages


Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

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