Thermal Challenges In Advanced Packaging


CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

Using FPGAs For AI


Artificial intelligence (AI) and machine learning (ML) are progressing at a rate that is outstripping Moore's Law. In fact, they now are evolving faster than silicon can be designed. The industry is looking at all possibilities to provide devices that have the necessary accuracy and performance, as well as a power budget that can be sustained. FPGAs are promising, but they also have some sig... » read more

Week In Review: IoT, Security, Autos


Internet of Things Amazon is expanding its IoT services. Alexa Voice Services will require less processing power on the device, moving from the 100MB of RAM and Arm Cortex A microprocessor to 1MB and an Arm Cortex-M. Amazon will do more of the processing in the cloud, enabling developers to add Alexa to smaller, single purpose devices. “It just opens up the what we call the real ambient inte... » read more

Verification In The Era Of Autonomous Driving, Artificial Intelligence And Machine Learning


The last couple of weeks have been busy with me participating on three panels that dealt with AI and machine learning in the contexts of automotive and aero/defense, in San Jose, Berlin and Detroit. The common theme? Data is indeed the new oil, and it messes with traditional value creation in electronics. Also, requirements for system design and verification are changing and there are completel... » read more

Thoroughly Verifying Complex SoCs


The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Electromagnetic Challenges In High-Speed Designs


ANSYS’ Anand Raman, senior director, and Nermin Selimovic, product sales specialist, talk with Semiconductor Engineering about how to deal with rising complexity and tighter tolerances in AI, 5G, high-speed SerDes and other chips developed at the latest process nodes where the emphasis is on high performance and low power. » read more

Die-To-Die Connectivity


Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how die-to-die communication is changing as Moore’s Law slows down, new use cases such as high-performance computing, AI SoCs, optical modules, and where the tradeoffs are for different applications.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTu... » read more

DRAM Scaling Challenges Grow


DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimate... » read more

A New Playbook For The AI Era


It’s Q4 in Silicon Valley, which means that most tech enterprises are in strategic planning mode, taking stock of where they are today and charting a course for where they want to be over the next few years. This year’s Q4 planning cycle needs to be a little different: the opportunities before us are an order of magnitude larger. So are the challenges. To get to where we need to be, our�... » read more

Why Standard Memory Choices Are So Confusing


System architects increasingly are developing custom memory architectures based upon specific use cases, adding to the complexity of the design process even though the basic memory building blocks have been around for more than half a century. The number of tradeoffs has skyrocketed along with the volume of data. Memory bandwidth is now a gating factor for applications, and traditional memor... » read more

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