Chip Industry Week In Review

By The SE Staff - 15 Sep, 2023 - Comments: 0

By Gregory Haley, Jesse Allen, and Liz Allan TSMC told equipment vendors to delay deliveries of the most advanced tools due to uncertain demand, according to Reuters. The news drove down stock prices of all the major equipment providers. On the other hand, TSMC said advanced packaging shortages will constrain AI chip shipments for the next 18 months, according to NikkeiAsia. The United St... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 14 Jan, 2022 - Comments: 0

Chipmakers, OEMs TSMC reported sales of $15.736 billion for the fourth quarter of 2021, up 5.7% sequentially. Net income grew 6.4% quarter-over-quarter. In the fourth quarter, shipments of 5nm accounted for 23% of total wafer revenues, while 7nm accounted for 27%. In the first quarter of 2022, TSMC’s sales are expected to be between $16.6 billion to $17.2 billion. TSMC also expects its 20... » read more

Pushing The Envelope With HBM2E Memory

By Joseph Rodriguez - 10 Dec, 2020 - Comments: 0

In September, Rambus announced the achievement of reaching 4 gigabits per second (Gbps) operation with our HBM2E memory interface. This milestone was demonstrated in silicon and required mastering substantial signal integrity and power integrity (SI/PI) challenges. The 4 Gbps mark represents a 20% rise from the previous maximum data rate of 3.2 Gbps for HBM2E. To date, the industry’s faste... » read more

Week In Review: Design, Low Power

By Jesse Allen - 11 Sep, 2020 - Comments: 0

Silvaco acquired the assets of Coupling Wave Solutions (CWS), including IP, patents, and analysis technologies. CWS provides tools for system-level interference analysis of complex SoCs that integrate analog, RF, and digital blocks. Silvaco said that the acquisition expands the company’s portfolio to address RF SOI (Silicon on Insulator) substrate analysis to accurately model and simulate noi... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 11 Sep, 2020 - Comments: 0

Synopsys announced an electronic and photonic co-design platform for photonic integrated circuit (PIC) design, layout implementation, and verification. The OptoCompiler provides schematic-driven layout and advanced photonic layout synthesis in the same platform. AI Rambus says it clocked 4.0 Gbps on its HBM2E memory interface (PHY and controller), which is a desirable speed for AI/ML traini... » read more

Optimizing Power For Learning At The Edge

By Brian Bailey - 08 Aug, 2019 - Comments: 0

Learning on the edge is seen as one of the Holy Grails of machine learning, but today even the cloud is struggling to get computation done using reasonable amounts of power. Power is the great enabler—or limiter—of the technology, and the industry is beginning to respond. "Power is like an inverse pyramid problem," says Johannes Stahl, senior director of product marketing at Synopsys. "T... » read more

Target: 50% Reduction In Memory Power

By Brian Bailey - 11 Apr, 2019 - Comments: 3

Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Using Analog For AI

By Brian Bailey - 14 Mar, 2019 - Comments: 0

If the only tool you have is a hammer, everything looks like a nail. But development of artificial intelligence (AI) applications and the compute platforms for them may be overlooking an alternative technology—analog. The semiconductor industry has a firm understanding of digital electronics and has been very successful making it scale. It is predictable, has good yield, and while every de... » read more

Alchip Minimizes Dynamic Power For High-Performance Computing ASICs

By Mentor, a Siemens Business - 09 May, 2018 - Comments: 0

Alchip, a fabless ASIC provider, focuses on high-performance computing ASICs. They decided to undertake a new project where they would employ the PowerPro RTL Low-Power Platform to reduce dynamic power consumption within their unique fishbone clock tree methodology. Could they achieve better power results using PowerPro and could they integrate the tool within their team and the existing design... » read more

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