tag: Aldec

When Is Verification Done?
By Ann Mutschler - 25 Feb, 2021 - Comments: 0

Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 29 Jan, 2021 - Comments: 0

Automotive/Mobility Chip makers in Taiwan will “do their best” to “squeeze out more chips” said Taiwan’s Minister of Economic Affairs Wang Mei-hua after having lunch with representatives of TSMC, UMC, Vanguard International Semiconductor Corp, and Powerchip Semiconductor Manufacturing Co., according to the Taipei Times. After the auto industry initially cut automotive chip orders bec... » read more

Big Changes In Verification
By Ann Mutschler - 28 Jan, 2021 - Comments: 0

Verification is undergoing fundamental change as chips become increasingly complex, heterogeneous, and integrated into larger systems. Tools, methodologies, and the mindset of verification engineers themselves are all shifting to adapt to these new designs, although with so many moving pieces this isn't always so easy to comprehend. Ferreting out bugs in a design now requires a multi-faceted... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Jan, 2021 - Comments: 0

Cadence will acquire NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. “Next-generation products and systems require comprehensive multi-physics engineering solutions encompassing IP, semiconductors, IC packaging, modules, board... » read more

Hard-To-Hire Engineering Jobs
By Susan Rambo - 13 Jan, 2021 - Comments: 3

While the pandemic has hurt many job sectors, the semiconductor industry can't get enough qualified people. And that shortage is expected to persist for years, as companies reach deep into untapped talent pools around the globe. Most in demand are experienced engineers and engineers with hybrid knowledge. Skills in machine learning and artificial intelligence are very desirable. Combined kno... » read more

RISC-V Verification Challenges Spread
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

Multicore Debug Evolves To The System-Level
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Dec, 2020 - Comments: 0

RISC-V RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, S... » read more

HDL Simulation Acceleration Solution For Microchip FPGA Designs
By Aldec - 23 Nov, 2020 - Comments: 0

Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Nov, 2020 - Comments: 0

Tools Mentor unveiled Tessent Streaming Scan Network software for its Tessent TestKompress software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources for a simplified bottom-up DFT flow. The bus-based scan data distribution architecture enables simultaneous testing of any number of cores and ... » read more

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