tag: Altera

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

Experts At The Table: Pain Points
By Ed Sperling - 27 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: What comes next requires a lot of guesswork in the design, do... » read more

Experts At The Table: Stacking The Deck
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler There is no doubt 3D stacking brings challenges not only from the design perspective, but also on the tool side. EDA vendors have been working for more than a few years to ready tools for stacked-die designs. How smooth the transition is, however, is a big question mark. Because the approach is new, not all the challenges are fully understood yet. And while most ED... » read more

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

Experts At The Table: Pain Points
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Gap Vs. Gap
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable. This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool cha... » read more

Getting Ready For Stacked Die
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary. All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, A... » read more

Where SoCs Don’t Go
By Ed Sperling - 22 Apr, 2010 - Comments: 0

By Pallab Chatterjee The National Association of Broadcaster show is the one place where you can be sure to find some of the most advanced technology on the planet—the kind of stuff used to broadcast, capture and edit 3D content. But while the market for this kind of technology is growing, the quantities of like products are still not high enough to warrant ASICs. It’s a world dominated... » read more

Integrated IP Goes Vertical
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways. It’s difficult to te... » read more

Making Connections
By Ed Sperling - 28 Oct, 2009 - Comments: 0

By Ed Sperling The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living. The numbe... » read more

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