The Week In Review: Design

By Jesse Allen - 10 Nov, 2017 - Comments: 0

IP Cryptographic flaws have been discovered in the IEEE P1735 standard for encrypting IP and managing access rights. A team from the University of Florida found "a surprising number of cryptographic mistakes in the standard. In the most egregious cases, these mistakes enable attack vectors that allow us to recover the entire underlying plaintext IP." The researchers warn that an adversary coul... » read more

Memory Test Challenges, Opportunities

By Jeff Dorsch - 18 Oct, 2017 - Comments: 0

The semiconductor capital equipment market is on fire, and the memory chip test equipment sector is no different. But it is getting much more difficult on the memory side. Memory test vendors are contending with next-generation devices, such as 3D NAND flash memories, HBM2 chips, low-power double-data-rate DRAMs, graphics DRAMs, phase-change memories, magnetoresistive RAMs, and resistive RAM... » read more

Power Modeling and Analysis

By Brian Bailey - 20 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], chief executive officer for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021"... » read more

Frenzy At 10/7nm

By Ann Mutschler - 14 Sep, 2017 - Comments: 1

The number of chipmakers rushing to 10/7nm is rising, despite a slowdown in Moore's Law scaling and the increased difficulty and cost of developing chips at the most advanced nodes. How long this trend continues remains to be seen. It's likely that 7/5nm will require new manufacturing equipment, tools, materials and transistor structures. Beyond that, there is no industry-accepted roadmap, m... » read more

What’s New At Hot Chips

By Jeff Dorsch - 25 Aug, 2017 - Comments: 0

By Jeff Dorsch & Ed Sperling Machine learning, artificial intelligence and neuromorphic computing took center stage at Hot Chips 2017 this week, a significant change from years past where the focus was on architectures that addressed improvements in speed and performance for standard compute problems. What is clear, given the focus of presentations, is that the bleeding edge of comput... » read more

Portable Stimulus Status Report

By Brian Bailey - 24 Aug, 2017 - Comments: 0

The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

Modeling Of The Electrical Performance Of The Power And Ground Supply For A PC Microprocessor On A Card

By Cadence - 09 Aug, 2017 - Comments: 0

The electrical characteristics of the power and ground supply of a PC microprocessor packaged in a Ball Grid Array (BGA) package mounted on a card are studied by dynamic electromagnetic field analysis. The effects of decoupling capacitors of different types and at different locations are investigated to achieve the objectives of low power and ground impedance and no or insignificant resonances ... » read more

The Secret Life Of Accelerators

By Ed Sperling - 27 Jul, 2017 - Comments: 0

Accelerator chips increasingly are providing the performance boost that device scaling once provided, changing basic assumptions about how data moves within an electronic system and where it should be processed. To the outside world, little appears to have changed. But beneath the glossy exterior, and almost always hidden from view, accelerator chips are becoming an integral part of most des... » read more

Start Your HBM/2.5D Design Today

By eSilicon - 28 Jun, 2017 - Comments: 0

High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. In June 2015, AMD introduced its Fiji processor, the first HBM 2.5D design, which comp... » read more

Architecture First, Node Second

By Ed Sperling - 15 Jun, 2017 - Comments: 0

What a difference a node makes. A couple of rather important changes have occurred in the move from 16/14 to 10/7nm (aside from more confusing naming conventions). First, companies that require more transistors—processor companies such as [getentity id="22846" e_name="Intel"], AMD, [getentity id="22306" comment="IBM"] and [getentity id="22676" e_name="Qualcomm"]—have come to grips with t... » read more

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Knowledge Centers
Entities, people and technologies explored

Intel Vs. Samsung Vs. TSMC

Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.

by Ed Sperling

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Chip Industry Week In Review

Softbank's acquisition; advanced packaging funding; glass substrates; engineered copper wire; semi equipment set new record; HBM4; AI chips rake in funding; X-ray inspection; apprenticeships.

by The SE Staff

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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