tag: analog

Verification Planning And Requirement Tracking For Analog Design
By Mentor, a Siemens Business - 24 Sep, 2014 - Comments: 0

Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend comm... » read more

IoT Brings Low Power To Forefront
By Brian Bailey - 11 Sep, 2014 - Comments: 0

Low power has become a primary design consideration over the past decade, driven by consumer portable devices packing in greater amounts of processing power and sophisticated communications, while at the same time providing extended battery life even though developments in battery technology have advanced little in the same timeframe. But the [getkc id="76" comment="Internet of Things"] (IoT) w... » read more

A Novel Approach To Dummy Fill For Analog Designs
By Mentor, a Siemens Business - 21 Aug, 2014 - Comments: 0

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

Improving 2.5D Components
By Ed Sperling - 07 Aug, 2014 - Comments: 1

A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Efficient Noise Analysis For Complex Non-Periodic Analog/RF Blocks
By Mentor, a Siemens Business - 25 Jun, 2014 - Comments: 0

Noise minimization is a required design objective for advanced analog and RF circuits. Unlike digital circuits, where noise is a second-order effect, noise in analog and RF circuits directly affects system performance metrics such as signal to noise ratio (SNR) and bit error rate (BER). Effective design optimization in the presence of random device noise is challenging because the noise sources... » read more

Extending UVM To Analog
By Ann Mutschler - 24 Apr, 2014 - Comments: 2

As SoC complexity has grown, so too has the need to model the analog/mixed-signal content in a similar way as the digital content to make simulation easier. One way to do this is within the context of the Universal Verification Methodology (UVM). In fact, this can and is being done today with UVM as it stands, according to a number of industry sources. However, there is also growing interest... » read more

Pain Management
By Ed Sperling - 10 Apr, 2014 - Comments: 0

In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

Test Challenges Rising For Mobile Devices
By Mark LaPedus - 20 Mar, 2014 - Comments: 0

Smartphone and tablets continue to advance at a dizzying pace. On the component side alone, the latest mobile devices are moving towards 64-bit application processors, multi-mode RF front-ends, higher-end cameras and flashy LCD screens. Some systems even boast fingerprint scanners and heart rate sensors. But an obvious part of the system continues to lag behind the curve—battery life. In r... » read more

Five Key Challenges In Designing With High-Speed Analog IP
By Various Writers - 12 Mar, 2014 - Comments: 0

There’s good reason why analog IC design is often considered to be more of an art than a science. Compared to their digital counterparts, analog components are much more sensitive to noise, distortion, and other errors. This white paper is filled with tips on meeting these challenges and speeding up your design cycle. To download this paper, click here. » read more

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