tag: analog

A Hierarchical And Tractable Mixed-Signal Verification Methodology For First-Generation Analog AI Processors
By Siemens EDA - 08 Mar, 2023 - Comments: 0

Artificial intelligence (AI) is now the key driving force behind advances in information technology, big data and the internet of things (IoT). It is a technology that is developing at a rapid pace, particularly when it comes to the field of deep learning. Researchers are continually creating new variants of deep learning that expand the capabilities of machine learning. But building systems th... » read more

Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning
By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning" was published by researchers at UT Austin and Analog Devices. Abstract "Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated s... » read more

Safety, Security, And Reliability Of AI In Autos
By Ed Sperling - 22 Feb, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about security, aging, and safety in automotive AI systems, with Geoff Tate, CEO of Flex Logix; Veerbhan Kheterpal, CEO of Quadric; Steve Teig, CEO of Perceive; and Kurt Busch, CEO of Syntiant. What follows are excerpts of that conversation, which was held in front of a live audience at DesignCon. Part one of this discussion is he... » read more

Comprehensive S-Parameter Verification Coverage With Analog FastSPICE
By Siemens EDA - 22 Dec, 2022 - Comments: 0

IC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies, multi-die chips, stacked 3D ICs and advanced packaging. Furthermore, design technology continues to progress towards supporting higher data rates to address the increasing demand for more and enhanced connectivity. We now must deal with much more... » read more

Repurposing Josephson Junctions At The Cell Boundaries For Fan-out (UCSB)
By Technical Paper Link - 16 Dec, 2022 - Comments: 0

A technical paper titled "Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions" was published by researchers at UC Santa Barbara.  The paper received an award at the Applied Superconductivity Conference in Oct 2022 and was highlighted in this UCSB news article. Abstract: "Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lo... » read more

3-to-1 Reconfigurable Analog Signal Modulation Circuit On A Single Device
By Technical Paper Link - 18 Nov, 2022 - Comments: 0

A new technical paper titled "Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor" was published by researchers at NaMLab gGmbH, GlobalFoundries, and TU Dresden. "Reconfigurable field effect transistors are an emerging class of electronic devices, which exploit a structure with multiple independent gates to selectively adjust the charge carrier ... » read more

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development
By Tom Fitzpatrick - 04 Oct, 2022 - Comments: 0

By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

Interactive Symmetry Checking Provides Faster, Easier Symmetry Verification For Analog And Custom IC Designs
By Siemens EDA - 22 Sep, 2022 - Comments: 0

Device symmetry ensures accurate, efficient performance of analog and custom IC designs. However, traditional physical verification for symmetry is complex and time-consuming. Calibre interactive symmetry checking runs inside the design environment to simplify and enhance IC symmetry verification. Design teams can use Calibre interactive symmetry checking to quickly and accurately analyze layou... » read more

Graph-Based, Formal Equivalence Checking Method
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new research paper titled "Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits" was published by researchers at University of Bremen and DFKI GmbH. Abstract: "Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level met... » read more

Detailed RF Characterization of Ultra-Thin Indium Oxide Transistors
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A new technical paper titled "Record RF Performance of Ultra-thin Indium Oxide Transistors with Buried-gate Structure" was published by researchers at Purdue University and won the 2022 Device Research Conference Best Student Paper Award (DRC 2022 held in June). According to this Purdue University news release, "In this work, the radio frequency (RF) performance of indium oxide transistors w... » read more

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