Blog Review: Oct. 15

By Ed Sperling - 15 Oct, 2014 - Comments: 0

Obesity makes your liver age faster, but you'll need a sophisticated biological clock to see that. Ansys' Bill Vandermark uncovers the top 5 engineering articles of the week. This one includes cyborg horses and an implanted prosthetic arm. Mentor's Colin Walls takes a look at "hard" and "soft" real time. It sounds like something out of a Salvador Dali painting. Rambus' Aharon Etengoff t... » read more

Will There Be A DDR5?

By Ed Sperling - 10 Oct, 2014 - Comments: 1

DDR4 rollouts have begun. And in the DRAM world that begs the question, 'What comes next?' The answer isn't so obvious. While there have been suggestions inside of JEDEC — the Joint Electron Device Engineering Council, which has overseen the standards for double-data-rate synchronous DRAM — to develop a DDR5 standard, it's not the only solution being considered. And in the minds of some... » read more

Architecture Versus Silicon

By Ann Mutschler - 09 Oct, 2014 - Comments: 0

For many, if not most designs today, power is everything. Determining where power is being lost is critical to making sure the design is optimized. So where to begin? To this end, it is useful to go back to the fundamentals of what power is and what power consumption is, noted Paul Traynar, software architect at [getentity id="22021" comment="ANSYS/Apache"]. “Power is proportional to capac... » read more

Software Before Hardware?

By Ed Sperling - 09 Oct, 2014 - Comments: 0

The emphasis on battery life in wearable electronics, including always-on sensors, and the cost of powering and cooling racks of servers inside of data centers, are beginning to impact the formula for designing systems. Power is now a critical design element, but it's also one of the most stubborn to tackle. While ASICs, SoCs and FPGAs all have focused on being able to efficiently run softwa... » read more

Optimizing Analog For Power At Advanced Nodes

By Ann Mutschler - 09 Oct, 2014 - Comments: 0

As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

Ubiquitous Trend In Design for Power (DFP) For IP And SoCs

By Vic Kulkarni - 09 Oct, 2014 - Comments: 0

Semiconductor design engineers must meet power specification thresholds, or power budgets, that are dictated by the electronic system vendors to whom they sell their products. Analyzing and reducing power across the board in all market segments has become a key requirement and a differentiator, especially over last 8 to 10 years for IP and IP-based SoC designers. Many products live and die due ... » read more

Energy Boost For Power Standards

By Brian Bailey - 09 Oct, 2014 - Comments: 0

If the amount of standards work and industry effort that is being expended on a given topic is any indicator of the growing importance of a design concern, then power has most certainly become the hottest topic in the industry. Thankfully, it seems as if everyone has learned their lessons from the CPF/[gettech id="31044" t_name="UPF"] struggles and is attempting to coordinate activities, while ... » read more

System-Aware SoC Power, Noise And Reliability Sign-off

By Ansys - 08 Oct, 2014 - Comments: 0

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

IoT Demands Correct By Construction Assembly

By Brian Bailey - 25 Sep, 2014 - Comments: 0

The article Limiters To The Internet Of Things outlined several factors that are slowing the rate of deployment for the [getkc id="76" kc_name="IoT"]. Those limiters are cost, power delivery and storage, standards, security, and the limits of your imagination. This article picks up on a comment made by [getperson id="11244" comment="Chris Rowen"], fellow at [getentity id="22032" e_name="Cadence... » read more

Blog Review: Sept. 24

By Ed Sperling - 24 Sep, 2014 - Comments: 0

Cadence’s Brian Fuller captures Chris Rowen’s phylum classifications for data-efficient design—lots of insects and much bigger but fewer mammals. There are cognitive layers in between, as well. Check out the chart. Mentor’s Robin Bornoff digs into thermal runaway and how to determine when it will occur—and burn up a chip. There’s a video to illustrate just what can go wrong. ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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