tag: ANSYS

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 13 Jun, 2013 - Comments: 0

In the first two parts of this series, we reviewed the challenges design teams face as they grapple with increasing power consumption, tighter schedules and the drive to reduce costs. Both a top-down and a bottom-up analysis framework were proposed to help control these challenges. In part 2 of this series, specific challenges were outlined including power budgeting, power and signal integrity,... » read more

The Week In Review: June 7
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling For all the hesitation about moving the Design Automation Conference to Austin, it turns out that Austin has a lot of hardware engineers. In fact they flooded into the conference, turning it into one of the most successful in recent years and setting new records in multiple areas. Even Texas Gov. Rick Perry showed up to see what all the fuss was about. Mentor Graphics added c... » read more

Executive Briefing: Andrew Yang
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Andrew Yang, president of ANSYS subsidiary Apache Design, sat down with Low-Power/High-Performance Engineering to talk about why power is becoming so important and where the future challenges lie. What follows are excerpts of that conversation. LPHP: What’s the most important issue these days for chipmakers? Yang: According to the feedback we’ve gotten from our customer... » read more

Technologies For Power, Signal, Thermal, And EMI Sign-Off
By Various Writers - 09 May, 2013 - Comments: 0

This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines. To download this white paper, click here. » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 09 May, 2013 - Comments: 0

Power efficiency, unrealistic schedules, and cost-down considerations are increasingly the top challenges design teams must meet to deliver next generation electronic systems, whether it is for the mobile, server, or automotive market. In addition, a successful chip tapeout does not guarantee the eventual end-product’s success—there are many variables to take into account. In the first p... » read more

Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology
By Various Writers - 11 Apr, 2013 - Comments: 0

To meet smart device requirements with high levels of sophistication from an exceedingly small device running off a battery, the underlying electronics must evolve at a rapid pace. To read more, click here. » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 11 Apr, 2013 - Comments: 0

By Aveek Sarkar Designing successful electronic systems that can meet the needs of a challenging and quickly evolving mobile market requires design teams to solve critical problems such as power efficiency, unrealistic schedules, and cost-down considerations. In this first of a three-part series, we will look at these challenges. Part 1: The Growing Challenges Designing electronic systems ... » read more

Shock Value
By Norman Chang - 14 Mar, 2013 - Comments: 0

By Norman Chang Chip-Package-System (CPS) ESD simulation enables system-wide ESD robustness validation, a common challenge in automotive and aerospace applications. To enable CPS ESD analysis requires an accurate chip electrostatic discharge (ESD) model and a comprehensive system-level ESD methodology. Using an accurate ESD chip model provides the following three benefits. First it helps de... » read more

New Issues In Signoff
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

RTL Design-For-Power Methodology
By Various Writers - 14 Feb, 2013 - Comments: 0

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To download this white paper, click here. » read more

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