tag: ANSYS

Chip Failures: Prevention And Responses Over Time
By Ed Sperling - 19 Mar, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the causes of chip failures, how to respond to them, and how that can change over time, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, hi... » read more

Blog Review: Mar. 19
By Jesse Allen - 19 Mar, 2025 - Comments: 0

Cadence's Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests. Siemens EDA's Stephen V. Chavez examines the use of blind and buried vias in high-density i... » read more

3D-IC For The Masses
By Brian Bailey - 13 Mar, 2025 - Comments: 0

The concepts of 3D-IC and chiplets have the whole industry excited. It potentially marks the next stage in the evolution of the IP industry, but so far, technical difficulties and cost have curtailed its usage to just a handful of companies. Even within those, they do not appear to be seeing benefits from heterogeneous integration or reuse. Attempts to make this happen are not new. "A decade... » read more

The Importance Of Safety Analysis In Automotive Systems Engineering
By Ka-lip Chu - 13 Mar, 2025 - Comments: 0

Over the years, automotive safety has maintained a top spot in the minds of original equipment manufacturers (OEMs). Self-driving vehicles, advanced driver assistance systems (ADAS), and AI-driven innovations designed to further protect us on the road are rapidly evolving. It’s been an exciting journey but not without some hiccups for automotive manufacturers along the way. For instance, a... » read more

Chiplets Add New Power Issues
By Ann Mutschler - 13 Mar, 2025 - Comments: 0

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

Integrating Data From Design, Manufacturing, And The Field
By Adam Kovac - 13 Mar, 2025 - Comments: 0

Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as dimensions become smaller, and as more features are added into devices — especially with heterogeneous assemblies of chiplets running some type of AI — the potential for thermally induced structur... » read more

Extracting Parasitic Impedance Of Semiconductor Power Modules
By Ansys - 12 Mar, 2025 - Comments: 0

As a key component in energy conversion system, power semiconductor devices are widely used in various applications, e.g., electric vehicles, renewable energy conversion, and uninterrupted power supplies. The trend for power converter design is always toward higher power density. Power modules that integrate multiple semiconductor devices can meet this demand. It also reduces the compl... » read more

Blog Review: Mar. 12
By Jesse Allen - 12 Mar, 2025 - Comments: 0

Cadence's P. Saisrinivas explains the relationship between drive strength and cell delay and why it is key to choose the appropriate drive strength to meet timing constraints while minimizing power and area. Siemens' Daniel Berger and Dirk Hartmann tackle the readout problem of accurately measuring the state of a quantum system after it has undergone a quantum computation, which becomes incr... » read more

Improving Verification Methodologies
By Brian Bailey - 27 Feb, 2025 - Comments: 0

Methodology improvements and automation are becoming pivotal for keeping pace with the growing complexity and breadth of the tasks assigned to verification teams, helping to compensate for lagging speed improvements in the tools. The problem with the tools is that many of them still run on single processor cores. Functional simulation, for example, cannot make use of an unlimited number of c... » read more

Multi-Die Design Complicates Data Management
By Adam Kovac - 27 Feb, 2025 - Comments: 0

The continued unbundling of SoCs into multi-die packages is increasing the complexity of those designs and the amount of design data that needs to be managed, stored, sorted, and analyzed. Simulations and test runs are generating increasing amounts of information. That raises questions about which data needs to be saved and for how long. During the design process, engineers now must wrestle ... » read more

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