Multi-Die Assemblies Complicate Parasitic Extraction


The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

Introducing a Digital Engineering Methodology To Aid All Engineers


A systems engineer developing a novel system-on-a-chip (SoC) design. A CFD engineer studying the airflow over the wing of a new electric airplane design. A safety engineer reviewing the design of a new pacemaker to confirm that it is compliant with existing regulations and requirements. What do all these people have in common? One connecting thread is the ever-present need to efficiently col... » read more

Mobile Chip Challenges In The AI Era


Leading smart phone vendors are struggling to keep pace with the rising compute and power demands of localized generative AI, standard phone functions, and the need to move more data back and forth between handsets and the cloud. In addition to edge functions, such as facial recognition and other on-device apps, phones must accommodate a continuous stream of new communications protocols, and... » read more

AR/VR Glasses Taking Shape With New Chips


More augmented reality (AR), virtual reality (VR), and mixed reality (MR) wearables are coming, but how they are connected, and where image and other data is processed, are still in flux. Ray-Ban Meta AI glasses, for example, look like classic eyeglasses, but they rely on a tethered smart phone for such functions as taking pictures, AI voice assistance, and object identification. In contrast... » read more

Blog Review: June 4


In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the implications of the software-defined transition, how it affects semiconductor development, and why it seems to be leading more companies towards developing their own silicon. Cadence’s Vinod Khera shows off a Linux-based audio development platform for prototyping AI audio applications with support for real-time ... » read more

Chip Industry Week in Review


The U.S. Commerce Department is tightening controls on EDA software sold to China by imposing additional license requirements. EDA companies are assessing the impact. Details on how broad the restrictions will be are still pending. The U.S. Federal Trade Commission (FTC) will require Synopsys and Ansys to divest key software assets — including optical, photonic, and RTL power analysis tool... » read more

A Balanced Approach To Verification


First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI


Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

Blog Review: May 28


Siemens’ Patrick Hope considers how to fully perform post-route signal integrity verification on PCB designs while maintaining the project’s timeline by implementing a progressive verification methodology that enables signal integrity experts to focus on issues that demand their expertise rather than simple errors. Cadence’s Vanessa Do checks out how CXL addresses the constant demand f... » read more

Blog Review: May 21


Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards. Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers... » read more

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