Chipmakers Getting Serious About Integrated Photonics


Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data. Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinne... » read more

Reducing Power Delivery Overhead


The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

Lower Power Chips: What To Watch Out For


Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

High-Fidelity Optical Edge Case Analyses For Lidar Simulation


Advanced driver assistance systems (ADAS) and autonomous vehicles (AV) rely on heavily on four main sensor modalities for perception: radars, cameras, ultrasonic and, most recently, lidars (light detection and ranging). Lidar is a crucial sensor to the ADAS toolset because it can measure precise three-dimensional images (point clouds) of everything from cars to traffic lights to pedestrians in ... » read more

When Failure Is Not An Option: Improving Medical Device Reliability


Medical electronics are expected to operate safely over extended periods of time to provide monitoring, therapeutic or life-sustaining functions for patients. Without built-in reliability, these devices could experience failures or malfunctions that greatly increase the possibility of infection or death. In the movie Apollo 13, NASA’s Gene Kranz (played by actor Ed Harris) made the phrase “... » read more

Blog Review: July 7


Cadence's Sangeeta Soni provides a primer on the PIPE SerDes architecture and some of the changes that can introduce verification challenges for SerDes compliant PHY and MAC devices. Siemens EDA's Chris Spear demystifies the $cast() method in SystemVerilog, which checks values at runtime rather than compile time, and gives some examples of when it is useful. Synopsys' Chris Clark warns th... » read more

5G Chips Add Test Challenges


The advent of chips supporting millimeter-wave (mmWave) 5G signals is creating a new set of design and testing challenges. Effects that could be ignored at lower frequencies are now important. Performing high-volume test of RF chips will require much more from automated test equipment (ATE) than is required for chips operating below 6 GHz. “MmWave design is a pretty old thing,” said Y... » read more

Week In Review: Design, Low Power


Tools Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (st... » read more

Week In Review: Auto, Security, Pervasive Computing


Security The U.S. government agencies put out a warning that Russian military has been using a Kubernetes cluster to attempt distributed and anonymized brute force access against hundreds of government and private sector targets worldwide. Department of Homeland Security (DHS)’s Cybersecurity and Infrastructure Security Agency (CISA), the Federal Bureau of Investigation (FBI), the National S... » read more

Blog Review: June 30


Siemens EDA's Chris Spear considers what classes should represent in SystemVerilog and offers two major categories along with some helpful UVM tips. Cadence's Paul McLellan listens in on keynotes at the recent TSMC Technology Symposium, including TSMC CEO C. C. Wei's introduction some of the fab's new offerings, such as an automotive-focused N5 process. Synopsys' Dennis Kengo Oka notes th... » read more

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