tag: ANSYS

Reusable Power Models
By Brian Bailey - 14 Aug, 2024 - Comments: 0

Power is not a new concern, and proprietary models are available for some tasks, but the industry lacks standardization. The Silicon Integration Initiative (Si2) is hoping to help resolve that with an upcoming release of IEEE 2416, based on its Unified Power Model (UPM) work. The creation of any model is not to be taken lightly. There is a cost to its creation, verification and maintenance. ... » read more

Power Delivery Challenged By Data Center Architectures
By Ann Mutschler - 08 Aug, 2024 - Comments: 0

Processor and data center architectures are changing in response to the higher voltage needs of servers running AI and large language models (LLMs). At one time, servers drew a few hundred watts for operation. But over the past few decades that has changed drastically due to a massive increase in the amount of data that needs to be processed and user demands to do it more quickly. NVIDIA's G... » read more

Voltage Drop Now Requires Dynamic Analysis
By Karen Heyman - 08 Aug, 2024 - Comments: 0

At one time a relatively infrequent occurrence, voltage drop is now a major impediment to reliability at advanced nodes. Decades ago, voltage drop was only an issue for very large and high-speed designs, where there was concern about supply lines delivering full voltage to transistors. As design margins have tightened in modern advanced designs, controlling voltage drop has become a requiremen... » read more

Powering The Future Of Flight: Designing A Hydrogen-Powered eVTOL
By Caty Fairclough - 08 Aug, 2024 - Comments: 0

A large, bustling city surrounds you — crowded streets and tall buildings reaching toward the sky. You’re late for an appointment. However, instead of hopping into a car, you look above for your ride: an electric vertical takeoff and landing (eVTOL) vehicle. It is a small aircraft that takes off and lands vertically like helicopters, uses sustainable electric propulsion systems, and is inte... » read more

Blog Review: Aug. 7
By Jesse Allen - 07 Aug, 2024 - Comments: 1

Synopsys' Jyotika Athavale and Randy Fish investigate the problem of silent data corruption caused by difficult-to-detect hardware defects that cause unnoticed errors in the data being processed and is becoming an increasingly pressing problem as computing scales massively at a rapid pace with the demands of AI. Siemens' Keith Felton suggests adopting physical design reuse circuits to provid... » read more

Decoding Glitch Power at the RTL Stage
By Ansys - 07 Aug, 2024 - Comments: 0

In the context of analyzing digital semiconductor circuits, a glitch is any unwanted or unused signal transition, or toggle. A glitch is often a transient signal that is much shorter than a clock period and therefore is not captured by the next register stage. We also encounter full transition glitches, or transport glitches, which refer to toggles in a data path circuit that cover a full clock... » read more

Chip Industry Week in Review
By The SE Staff - 02 Aug, 2024 - Comments: 0

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Blog Review: July 31
By Jesse Allen - 31 Jul, 2024 - Comments: 0

Cadence's Jasmine Makhija explains how to boost the performance of CXL 3.0 by using NOP (No Operation) Insertion Hints in latency-optimized 256B Flit Mode, which enables the system to quickly revert to the low-latency path after temporarily switching to a higher-latency path due to error correction needs. Synopsys' Robert Fey finds that by automatically and dynamically linking requirements a... » read more

Chip Industry Week In Review
By The SE Staff - 26 Jul, 2024 - Comments: 0

The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Will AI Disrupt EDA?
By Brian Bailey - 25 Jul, 2024 - Comments: 1

Generative AI has disrupted search, it is transforming the computing landscape, and now it's threatening to disrupt EDA. But despite the buzz and the broad pronouncements of radical changes ahead, it remains unclear where it will have impact and how deep any changes will be. EDA has two primary roles — automation and optimization. Many of the optimization problems are NP hard, which means ... » read more

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