tag: ANSYS

Blog Review: Sept. 16
By Jesse Allen - 16 Sep, 2020 - Comments: 0

Cadence's Paul McLellan checks out what's new for TSMC's advanced packaging solutions and the ultra-low power, RF, eNVM, and CMOS image sensor specialty processes. Mentor's Ron Press points to an automated solution to measuring pattern value that provides a consistent, “apples to apples” assessment of patterns detecting defects based on the likelihood the physical defects occurring. S... » read more

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

Dealing With Device Aging At Advanced Nodes
By Ann Mutschler - 10 Sep, 2020 - Comments: 0

Premature aging of circuits is becoming troublesome at advanced nodes, where it increasingly is complicated by new market demands, more stress from heat, and tighter tolerances due to increased density and thinner dielectrics. In the past, aging and stress largely were separate challenges. Those lines are starting to blur for a number of reasons. Among them: In automotive, advanced-node... » read more

Learn How To Streamline Design Flows And Reduce Design Cost
By Marc Swinnen - 10 Sep, 2020 - Comments: 0

I’m excited to announce that general registration is now open for the new Ansys IDEAS Digital Forum!  IDEAS, hosted by Ansys Semiconductor, is a virtual gathering of top industry executives, thought leaders, and designers from some of the biggest IP, chip design, semiconductor foundry and electronic system companies in the world. Log in to IDEAS to join with your peers to listen to industry ... » read more

Blog Review: Sept. 9
By Jesse Allen - 09 Sep, 2020 - Comments: 0

Mentor's Jacob Wiltgen considers the recent advances in safety critical engineering and how automated the lifecycle can become, where tools form a set of checks and balances to ensure the accuracy of results. Cadence's Paul McLellan finds out what's new at TSMC, including a new R&D center, fab construction, capacity increases for existing nodes, and what the company sees for beyond its N... » read more

Electro-Thermal Signoff For Next Gen 3DICs
By Ansys - 09 Sep, 2020 - Comments: 0

Multi-die designs, 2.5D and 3D, have been rising in popularity as they offer tremendously increased levels of integration, a smaller footprint, performance gains and more. While they are attractive for many applications, they also create design bottlenecks in the areas of thermal management and power delivery. For 3DICs, in addition to the complex SoC/PCB interactions seen in their 2D counterpa... » read more

Far Out AI In Remote Locations
By SE Staff - 08 Sep, 2020 - Comments: 0

There really isn’t anything that you can do on Earth with electronics that you can’t do in space, but it certainly can be a lot harder and take longer to fix is something goes wrong. And as more intelligent electronics are launched into space, the concern over potential failures is growing. AI inferencing has been pushing out further for some time, and it is starting to redefine what con... » read more

Blog Review: Sept. 2
By Jesse Allen - 02 Sep, 2020 - Comments: 0

Arm's Pranay Prabhat highlights research into zero-power or low-power sensing devices and work toward designing a microcontroller that could fit with DARPA N-ZERO sensors. Mentor's Shivani Joshi provides a primer on the ODB++ standard data exchange file format that generates PCB design data files for use in fabrication, assembly, and test. Cadence's Paul McLellan shares some highlights fr... » read more

New Architectures, Much Faster Chips
By Ed Sperling and Ann Mutschler - 31 Aug, 2020 - Comments: 0

The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Aug, 2020 - Comments: 0

Tools & IP Monozukuri unveiled its IC/Package co-design tool, GENIO. GENIO integrates existing silicon and package EDA flows to create full co-design and I/O optimization of complex multi-chip designs.  It works seamlessly across all existing EDA flows and comprises floor planning, I/O planning and end-to-end interconnect planning combined with cross-hierarchical pathfinding optimization.... » read more

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