Power And Signal Line Electromigration


Power and Signal Line Electromigration Design and Reliability Validation Challenges for the 28nm-era Reliability verification is an important aspect in the design and development of an integrated circuit to guarantee its continued functioning over years of production use. One critical area of reliability verification is electromigration (EM) check analysis to ensure that the wires and vias u... » read more

Defining Power Intent


By Ann Steffora Mutschler Designing power-sensitive SoCs has never been more challenging given the tremendous demand for power efficiency in applications ranging from smart phones to servers inside data centers. That makes describing the power control architecture of a chip through power intent essential. Specifically, explained Will Ruby, senior director of product engineering and applicat... » read more

Can IP Be Standardized In Low-Power Designs?


By Ann Steffora Mutschler SoC designers are beginning to embrace low power formats UPF (IEEE P1801) and the Common Power Format (CPF) to express power intent, but are these efforts enough to create standardized IP in low power designs? Mike Brogley, IP and solutions product marketing manager at Actel, believes it is possible. “Yes, IP can be standardized, but the main driver in low-pow... » read more

Rethinking Models


By Ed Sperling The move to future process nodes will require more than just new materials, better layouts and higher levels of abstraction. It also will require a fundamental re-thinking of how high-level architectural models are created and what’s included in them. While the Transaction-Level Modeling (TLM) 2.0 standard has provided significant improvements for everything from layout to ... » read more

Experts At The Table: The Power Problem


Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that convers... » read more

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