tag: Apache Design

New Incentives For Lowering Power
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Despite all the focus by design teams on lowering power over the past few years, in many applications power is still the last consideration for many companies in the power-performance-area equation. That’s beginning to change, however, even for applications that in the past have not been particularly power-sensitive. There are several reasons for this shift. No. 1 on the li... » read more

Signal Integrity’s Growing Complexity
By Matt Elmore - 08 Nov, 2012 - Comments: 0

By Matt Elmore In Part 1, we reviewed the importance of simultaneous switching output (SSO) timing and the challenges associated with double data rate (DDR) simulation complexity. DDR memory interfacing has reached incredible levels of performance (17 Gb/s), requiring precise quantification and reduction of noise. In order to account for each noise contributor, we must model systems end-to-... » read more

Design For Power
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different. While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality,... » read more

Design For Reliability
By Arvind Vel - 11 Oct, 2012 - Comments: 0

By Arvind Shanmugavel Faster processors, lowered power targets and shrinking technology have increased the complexity of integrated circuit (IC) reliability analysis. With the 20nm node becoming mainstream, IC design teams are fast re-tooling their analysis methodologies to simulate and capture various reliability failure mechanisms. Electromigration (EM) analysis, thermal analysis and Electro... » read more

Signal Integrity’s Growing Complexity
By Matt Elmore - 13 Sep, 2012 - Comments: 0

By Matt Elmore While in the market for a memory upgrade recently, I was surprised by the availability of commercial DDR memories. You can get 8GB of DDR3 memory, transferring 17GB/s, relatively inexpensively. The progress in memory design is outstanding. From smartphones to gaming PCs, quick communication between the IC and off-chip memory is key to enabling the performance we demand in the... » read more

Preparing For 3DX
By Aveek Sarkar - 09 Aug, 2012 - Comments: 0

By Aveek Sarkar Undoubtedly we live in the age of mobility—smartphones, tablets, and ultra-books have transformed the way we work, live, and communicate. The worldwide smartphone market’s forecasted 24% CAGR, between 2010 and 2015 provides unique opportunities1. In emerging economies, more than 1 billion consumers are ready for the next new mobile platform2. Success in this market demands ... » read more

Meeting Emerging Needs For Next-Generation 3D-IC And Sub-20nm Designs
By Various Writers - 09 Aug, 2012 - Comments: 0

To remain competitive, IC designers must meet performance, power and price goals. However, these mutually conflicting goals require design techniques including 3D stacked-die architectures that will help meet performance and power targets by extending the integration capabilities beyond traditional SoC methodologies. To download this white paper, click here. » read more

Experts At The Table: Pain Points
By Ed Sperling - 27 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: What comes next requires a lot of guesswork in the design, do... » read more

Smarter Co-design With Models
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler IC, package and PCB co-design methodologies are starting to be adopted by semiconductor companies. However, the existing die abstract file used in these flows to exchange data between the IC designer and the downstream package design team may not contain enough detail to drive advanced planning and optimization with the package and PCB interfaces. Engineering teams... » read more

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

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