Week In Review: Auto, Security, Pervasive Computing


Security A new security annotation standard for hardware IP is now available for download at no cost. The board of directors of the Accellera Systems Initiative, the non-profit EDA- and IP-standards organization, approved the release of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. The standard, developed by Accellera’s IP Security Assurance (IPSA) Working ... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs More delays and product woes at Intel. “INTC disclosed that it is delaying the launch of its next-generation Xeon server processor Sapphire Rapids (10nm) from the end of this year to 1Q22 due to additional validation needed for the chip,” said John Vinh, an analyst at KeyBanc, in a research note. “Production is expected to begin in 1Q22, with the ramp expected to begi... » read more

CEO Outlook: More Data, More Integration, Same Deadlines


Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Fan-Out Packaging Options Grow


Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Shifting Toward Data-Driven Chip Architectures


An explosion in data is forcing chipmakers to rethink where to process data, which are the best types of processors and memories for different types of data, and how to structure, partition and prioritize the movement of raw and processed data. New chips from systems companies such as Google, Facebook, Alibaba, and IBM all incorporate this approach. So do those developed by vendors like Appl... » read more

Pushing The Limits Of Hardware-Assisted Verification


As semiconductor complexity continues to escalate, so does the reliance on hardware-assisted simulation, emulation, and prototyping. Since chip design first began, engineers have complained their design goals exceeded the capabilities of the tools. This is especially evident in verification and debug, which continue to dominate the design cycle. Big-iron tooling has enabled design teams to k... » read more

The Increasingly Uneven Race To 3nm/2nm


Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

Advanced Packaging’s Next Wave


Packaging houses are readying the next wave of advanced packages, enabling new system-level chip designs for a range of applications. These advanced packages involve a range of technologies, such as 2.5D/3D, chiplets, fan-out and system-in-package (SiP). Each of these, in turn, offers an array of options for assembling and integrating complex dies in an advanced package, providing chip custo... » read more

Week In Review: Manufacturing, Test


Government policy Semiconductor companies as well hardware and software vendors have announced the formation of the Semiconductors in America Coalition (SIAC). The group called on congressional leaders to appropriate $50 billion for U.S. manufacturing incentives and research initiatives. SIAC’s mission is to advance federal policies that promote semiconductor manufacturing and research in th... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Intel wants $9.7 billion in subsidies for use in building a leading-edge fab in Europe, according to a report from Reuters. As reported, in March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Eighteen members of the European Union recently launched an ... » read more

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