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Week In Review: Auto, Security, Pervasive Computing

Security IP hardware standard; Xilinx HBM Versal SoC; design tool improvements.

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Security
A new security annotation standard for hardware IP is now available for download at no cost. The board of directors of the Accellera Systems Initiative, the non-profit EDA- and IP-standards organization, approved the release of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. The standard, developed by Accellera’s IP Security Assurance (IPSA) Working Group, provides a non-tool specific that defines IP hardware issues and how to flag them

“I am very proud of the work our team has done to get this standard out into the community,” said Brent Sherman, IPSA Working Group Chair, in a press release. “To develop SA-EDI, we focused on using existing standards that pertain to IP specification, design, verification, and integration where security risk is a significant concern, as well as known security concerns. Using this information, we were able to develop a standard that is low overhead, non-disruptive, and scalable across multiple target implementations. I look forward to the feedback from the community as we continue to evolve the standard.”

The working group chair is Brent Sherman of Intel and vice chair is Mike Borza of Synopsys.

Pervasive computing — IoT, edge, cloud, data center, and back
Xilinx added a high-bandwidth memory series to its Versal adaptive compute acceleration platform (ACAP) family, with fast memory for data center and network operators, built on 7nm node. The Versal HBM has advanced HBM2e DRAM, with 820GB/s of throughput and 32GB of capacity. When compared with DDR5 implementations, Xilinx says the HBM2e DRAM is giving 8X more memory bandwidth and 63% lower power. Secure connectivity and adaptive computing are other features. The series offers 5.6Tb/s of serial bandwidth with 112Gb/s PAM4 transceivers, 2.4Tb/s of scalable Ethernet bandwidth, 1.2Tb/s of line rate encryption throughput, 600Gb/s of Interlaken connectivity, and 1.5Tb/s of PCIe Gen5 bandwidth with built-in DMA, supporting both CCIX and CXL. The chip is designed to accelerate a range of workloads with large data sets, integrating adaptable engines for low-latency hardware parallelism, DSP engines for AI inference and signal processing, and scalar engines for embedded compute, platform management, and secure boot and configuration. Unlike fixed function accelerators, the Versal HBM series can dynamically reconfigureable hardware in milliseconds to adapt with evolving algorithms and emerging protocols, which Xilinx says eliminates the need for hardware redesign and re-deployment. The series will begin sampling in the first half of 2022, but some early evaluation boards and prototyping are available now.

Automotive, transportation
Cadence and UMC have optimized Cadence’s full digital design flow — for use on UMC’s 22ULP/ULL process technologies. UMC also replaced its library characterization tool with Cadence Liberate Characterization, which, the foundry said in its press release “is the foundation of the broader digital full flow and a critical piece that enables advanced timing and power analysis, optimization and signoff flows.” Automotive, along with advanced consumer and 5G, use 22ULP/ULL, a mature node. The new design flow has more tools for digital ultra-low-power device signoffs.

Siemens released an updated version of Parasolid, a physical modeling program of systems that is part of Siemens Xcelerator portfolio. The software is used by CAD/CAM/CAE/AEC software vendors. The update offers new modeling features and can work, says one customer, on Parasolid can be used on Apple‘s new M1 chip.

Through a year-old partnership between Siemens and business software company SAP, the companies released a roadmap for getting SAP S/4HANA and Siemens’ Teamcenter software to talk. Bringing these traditionally siloed systems together will breakdown barriers between engineers and the business side, Siemens hopes. Such an arrangement could help companies build tools for the safety-aware culture needed for compliances, such as ISO26262.

People, companies
IBM named Hongmei Li as its representative to the Si2 OpenAccess Coalition. Li manages the Product Design Enablement Group in IBM’s electronic design automation organization. She replaces Paul Stabler, a long-time supporter of OpenAccess activities, who is retiring from IBM.

Advantest says it is expanding its presence in India and has rebranded its subsidiary in Chennai, Tamil Nadu, India. On June 18, 2021, w2bi Mobile Technologies Pvt. Ltd. (WMTI), became Advantest India Private Limited (AIN), a wholly owned subsidiary of Advantest America, Inc.

Ansys is offering students in its electronics design platform for a free software download, expanding students’ online access to simulation tools that include Ansys HFSS, Ansys Maxwell, Ansys Q3D Extractor, and Ansys Icepak. This design platform is new addition to Ansys’ Academic Program, which is used in more than 2,750 universities around the world.

Read the most recent Automotive, Security, & Pervasive Computing newsletter. Check out job, event, and webinar Boards: Find industry jobs and upcoming conferences and webinars all in one place on Semiconductor Engineering. Knowledge Center: Boost your semiconductor industry knowledge. Videos: See the latest Semiconductor Engineering videos.

 



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