Week In Review: Semiconductor Manufacturing, Test


Semiconductor Research Corporation (SRC) released an interim roadmap for Microelectronic and Advanced Packaging Technologies (MPAT) that targets 10- to 15-year goals for 3D integration and multi-chiplet packaging. The roadmap is open for comments. Participants in the MPAT include AMD, IBM, Intel, Texas Instruments, Purdue University, SUNY Binghamton and the Georgia Institute of Technology. It i... » read more

Week In Review: Semiconductor Manufacturing & Test


The Biden Administration’s export bans for semiconductor manufacturing equipment are delaying expansion plans for Chinese chipmakers, Nikkei Asia reports. Yangtze Memory Technologies (YMTC) has halted work on its second memory plant near Wuhan, and ChangXin Memory Technologies (CMTX) says its second production facility, slated to open in 2023, will be delayed until 2024 or 2025. In an effo... » read more

As Chiplets Go Mainstream, Chip Industry Players Collaborate to Overcome New Development Challenges


The semiconductor industry is building a comprehensive chiplet ecosystem to seize on the advantages of the devices over traditional monolithic system-on-chips (SoCs) such as improved performance, lower power consumption, and greater design flexibility. With heterogeneous integration (HI) presenting significant challenges, collaboration to fulfill the potential of chiplets has become even more i... » read more

The Physics Of Ferroelectrics


The physics of ferroelectric materials is a large topic — too large for comprehensive coverage in a single article. While researching my recent article on negative capacitance, I found a number of papers that might be of interest to readers seeking more depth. Researchers in Japan used ferroelectric BiFeO3 to control the behavior of CaMnO3, a Mott insulator. Changing the polarization of th... » read more

Supply Chain Collaboration Key To Making Chip Industry More Sustainable


Coming in the wake of the COP27, the Smart and Green Manufacturing Summit at SEMICON Europa 2022 (Munich, 15-17 November) had a timely focus on the semiconductor industry’s contribution to meeting the United Nations’ target of limiting global warming to 1.5°C above pre-industrial levels. However, in an industry as large and valuable as semiconductors, social as well as environmental imp... » read more

Metrology Options Increase As Device Needs Shift


Semiconductor fabs are taking an ‘all hands on deck’ approach to solving tough metrology and yield management challenges, combining tools, processes, and other technologies as the chip industry transitions to nanosheet transistors on the front end and heterogenous integration on the back end. Optical and e-beam tools are being extended, while X-ray inspection is being added on a case-by-... » read more

Week In Review: Semiconductor Manufacturing, Test


SEMI , SEMI Europe and European Commission representatives, in consultation with semiconductor industry stakeholders, proposed initiatives to overcome the skills shortage in Europe’s microelectronics industry: Create an industry image campaign to raise public awareness on how technology is shaping the future, and how workers can establish careers in the semiconductor industry. Remove ... » read more

Week In Review: Semiconductor Manufacturing, Test


The CHIPS Act sparked $200 billion in private investments for U.S. semiconductor production, including 40 new semiconductor ecosystem projects, according to SIA. China is working toward self-sufficiency, with plans to invest more than 1 trillion yuan ($143 billion) to support domestic semiconductor production, according to Reuters. Arm said that Britain and the U.S. would not approve license... » read more

How Far Will Copper Interconnects Scale?


As leading chipmakers continue to scale finFETs — and soon nanosheet transistors — to ever-tighter pitches, the smallest metal lines eventually will become untenable using copper with its liner and barrier metals. What comes next, and when, is still to be determined. There are multiple options being explored, each with its own set of tradeoffs. Ever since IBM introduced the industry to c... » read more

Challenges In Backside Power Delivery


One of the key technologies to enable scaling below 3nm involves delivering of power on the backside of a chip. This novel approach enhances signal integrity and reduces routing congestion, but it also creates some new challenges for which today there are no simple solutions. Backside power delivery (BPD) eliminates the need to share interconnect resources between signal and power lines on t... » read more

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