Week In Review: Semiconductor Manufacturing, Test

U.S. export restrictions update, Samsung debuts 12nm DDR5, Intel’s graphic unit split, Nova’s Raman platform, European talent initiative.


SEMI , SEMI Europe and European Commission representatives, in consultation with semiconductor industry stakeholders, proposed initiatives to overcome the skills shortage in Europe’s microelectronics industry:

  • Create an industry image campaign to raise public awareness on how technology is shaping the future, and how workers can establish careers in the semiconductor industry.
  • Remove barriers to entry in the industry for top university graduates in part by retooling immigration policies.
  • Harmonize workforce development initiatives within Europe and create a European University Network for Microelectronics with a focus on internship and work opportunities for students.
  • Inspire children and teens to pursue STEM education, recruit more STEM teachers, and replicate existing talent development initiatives such as chip design competitions.

The U.S. added YMTC and Chinese AI chip developer Cambricon Technologies, among dozens of other companies from China and across the globe, to the trade-restrictions Entity List. One result could be YMTC’s abandonment of the market for 3D NAND Flash by 2024, according to TrendForce. In addition, because the U.S. alleges that Cambricon, a linchpin of China’s AI efforts, has links with the Chinese military and defense industry, it is now subject to the even stricter Foreign Direct Product Rule, along with 20 other companies. The U.S. also removed 27 other Chinese entities from the so-called unverified list thanks to successful site visits.

Taiwan said it would fine Foxconn for an unauthorized investment in Chinese chipmaker Tsinghua Unigroup even after the Taiwanese firm said it would be selling the stake. Reuters previously reported that the company could be fined up to T$25 million ($813,749).

Samsung announced its 16-gigabit DDR5 DRAM built using the industry’s first 12nm-class process technology, as well as the completion of product evaluation for compatibility with AMD. Made possible through the use of a new high-k material and proprietary design technology, combined with multi-layer EUV lithography, the new DRAM features the industry’s highest die density, which enables a 20% gain in wafer productivity, while consuming up to 23% less power. Volume production will begin in 2023.

Sony is considering building a new plant for smartphone image sensors in Japan’s Kumamoto prefecture, sourcing chips from TSMC’s planned fabrication facility in the area, according to Nikkei Asia.

Applied Materials plans to build a next-generation R&D center in Sunnyvale, California, and add equipment manufacturing capacity at its facilities in Austin, Texas and in Singapore. For its R&D center, the company expects support from the CHIPS and Science Act and the State of California through the Governor’s Office of Business and Economic Development (GO-Biz) California Competes Grant awarded earlier this year.

Intel is splitting its graphic chips unit into two, the company said on Wednesday, as it realigns the business to better compete with NVIDIA and AMD. The consumer graphics unit will be combined with Intel’s client computing group, which makes chips for personal computers, while accelerated computing teams will join its data center and AI business. “I don’t think it changes much (if anything) other than aligning the products with the respective sales organizations they fit with versus having them as a discrete segment,” Wedbush Securities analyst Matthew Bryson told Reuters.


Japanese semiconductor manufacturer PEZY Computing will use proteanTecs2.5D interconnect monitoring solution for die-to-die (D2D) connectivity in its next-generation processors.

A leading global logic manufacturer recently selected Nova‘s Raman spectroscopy system for its next-generation IC development. The technology performs non-destructive, in-die characterization of stress, strain and defectivity with high sensitivity.

Hitachi High-Tech launched a new optical wafer inspection system for detecting 20nm and smaller particles and defects on unpatterned wafers. It features a new high-output, short-wavelength laser that improves throughput by 2.5X relative to its previous generation systems.


Graphene for electronics is making strides toward ISO standards, according to discussions among the Graphene Council, NIST, and commercial entities.

NIST entered into a cooperative research and development agreement with AIM Photonics, a New York-based public-private partnership, to design electrical “calibration structures” that can be used to measure and test the electronic performance of photonic chips. The goal is improved design and test of chips capable of 110 GHz operation. Most current photonic chips operate at ∼25 GHz.

Inspired by the Semiconductor Electronics Education Committee (SEEC), which produced a series of books in the 1960s that sparked the microelectronic revolution, Purdue University’s College of Engineering, in partnership with World Scientific and the American Semiconductor Academy (ASA) Initiative, has announced the New Era Electronics: A Lecture Notes Series, a 21st century continuation of the SEEC notes.

Further reading

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Upcoming events:

  • CES 2023, Jan. 5-8, 2023 (Las Vegas, NV)
  • Industry Strategy Symposium (ISS 2023), Jan. 8-11, 2023 (Half Moon Bay, CA)
  • IPC 2023, Jan. 21-26 (San Diego, CA)
  • First Annual Chiplet Summit, Jan. 24-26, 2023 (San Jose, CA)
  • SPIE Photonics West, Jan. 28-Feb. 2, 2023 (San Francisco, CA)
  • Advanced Packaging for Medical Microelectronics, Feb. 2-3 (San Diego, CA)
  • ISS Europe, Feb. 15-16 (Vienna, Austria)

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