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Chip Industry Heads Toward $1T


The chip industry is on track to hit $1 trillion sometime over the next decade, and while the exact timing depends on a variety of factors, the trend line appears to be stable. The digitization of data, the digitalization of technology, and the expansion into new and existing markets, collectively are expected to drive chip industry growth for years to come. Exactly when the IC world will to... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part I


The traditional processors designed for general-purpose applications struggle to meet the computing demands and power budgets of artificial intelligence (AI) or machine leaning (ML) applications. Several semiconductor design companies are now developing dedicated AI/ML accelerators that are optimized for specific workloads such that they deliver much higher processing capabilities with much low... » read more

Domain-Specific Design Drives EDA Changes


The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

What Is An xPU?


Almost every day there is an announcement about a new processor architecture, and it is given a three-letter acronym — TPU, IPU, NPU. But what really distinguishes them? Are there really that many unique processor architectures, or is something else happening? In 2018, John L. Hennessy and David A. Patterson delivered the Turing lecture entitled, "A New Golden Age for Computer Architecture... » read more

The Next Generation Of General-Purpose Compute At Hot Chips


At the recent HOT CHIPS, the first day opened with the chips that you first think of when you hear the word processor. These are the next generation of chips from the likes of Intel, AMD, and IBM. There were lots of other chips too, such as Arm's Neoverse N2, and NVIDIA's new data-processing unit (DPU), or AMD's next-generation graphics architecture. But for this post, anyway, I'm going to focu... » read more

CEO Outlook: More Data, More Integration, Same Deadlines


Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Von Neumann Upset


My recent article about the von Neumann architecture received some quite passionate responses, including one that thought I was attempting to slight the person. That was most certainly not the intent, given that the invention enabled a period of very rapid advancement in computers and technology in general. The process of invention and engineering are both quite similar and yet different. In... » read more

Is Computing Facing An Energy Crisis?


Is the end near? If the topic is energy efficiency gains in computing, the answer depends on whom you ask. The steady increase in performance per watt over the decades has been one of the most important drivers in our industry. Last year I was thumbing through a neighbor’s 1967 Motorola IC catalog that featured such space age wonders as a small control chip of the sort that went into th... » read more

Better Security, Lower Cost


For years, chipmakers have marginalized security in chips, relying instead on software solutions. Eventually that approach caught up with them, creating near panic in a scramble to plug weaknesses involving speculative execution and branch prediction, as well as the ability to read the data from chips with commercially available tools such as optical probes. There were several reasons for th... » read more

Performance Metrics For Convolutional Neural Network Accelerators


Across the industry, there are few benchmarks that customers and potential end users can employ to evaluate an inference acceleration solution end-to-end. Early on in this space, the performance of an accelerator was measured as a single number: TOPs. However, the limitations of using a single number has been covered in detail in the past by previous blogs. Nevertheless, if the method of cal... » read more

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