Better Security, Lower Cost


For years, chipmakers have marginalized security in chips, relying instead on software solutions. Eventually that approach caught up with them, creating near panic in a scramble to plug weaknesses involving speculative execution and branch prediction, as well as the ability to read the data from chips with commercially available tools such as optical probes. There were several reasons for th... » read more

Performance Metrics For Convolutional Neural Network Accelerators


Across the industry, there are few benchmarks that customers and potential end users can employ to evaluate an inference acceleration solution end-to-end. Early on in this space, the performance of an accelerator was measured as a single number: TOPs. However, the limitations of using a single number has been covered in detail in the past by previous blogs. Nevertheless, if the method of cal... » read more

Engineering Within Constraints


One of the themes of DAC this year was the next phase of machine learning. It is as if CNNs and RNNs officially have migrated from the research community and all that is left now is optimization. The academics need something new. Quite correctly, they have identified power as the biggest problem associated with learning and inferencing today, and a large part of that problem is associated with ... » read more

An Automotive Value Chain In Flux


When companies view suppliers from inside their specialized niches, it is tempting to imagine the business world will continue as-is, with just minimal improvements each year. But in the automotive value chain, this no longer holds. The rapid pace of innovation around intelligent systems in cars is disrupting the business flow. Back in simpler times, semiconductor companies would work with Tier... » read more

Is There Finally A Silver Bullet For Software?


As I am in Nuremberg for the annual embedded world conference, the overall mood here seemed a bit muted and slow on day one. There are rumors of 200 exhibitors of the roughly 1100 having pulled out due to the global health situation—we are all asked not to shake hands and smile instead—and the rainy weather doesn't help much either. With the weather turning to snow on day two, the attendanc... » read more

Co-Design For The AI Era


Welcome to the second piece in our blog series examining how the computing industry can work in new ways to enable the AI Era. In our first blog, my colleague Ellie Yieh described the enormous opportunities and challenges facing the industry as we enter a new decade, and she offered a path for accelerating innovation—from materials to systems—based on a “New Playbook” for driving im... » read more

High-Performance DSP And Control Processing For Complex 5G Requirements


In the early 2000s, digital signal processors (DSP) were simple in architecture and limited in performance, but complex in programming. However, they evolved to meet of the increased performance requirements of 3G cellular baseband modem applications. A typical 3G modem system would have a single DSP optimized for dual/quad SIMD MAC performance with basic DSP filter instructions like Fast Fouri... » read more

Breaking The AI Memory Bottleneck


In the long unfolding arc of technology innovation, artificial intelligence (AI) looms as immense. In its quest to mimic human behavior, the technology touches energy, agriculture, manufacturing, logistics, healthcare, construction, transportation and nearly every other imaginable industry – a defining role that promises to fast track the fourth Industrial Revolution. And if the industry orac... » read more

Playing Into China’s Hands


The fallout over blacklisting Huawei in particular, and China in general, has set the tone for a nasty global race. But it is almost certain to produce a different result than the proponents of a trade war are expecting. The idea behind tariffs and the blacklisting of Huawei is to starve China of vital technology. So far, the impact has been minimal. Reports from inside of China are equa... » read more

Memory Architectures In AI: One Size Doesn’t Fit All


In the world of regular computing, we are used to certain ways of architecting for memory access to meet latency, bandwidth and power goals. These have evolved over many years to give us the multiple layers of caching and hardware cache-coherency management schemes which are now so familiar. Machine learning (ML) has introduced new complications in this area for multiple reasons. AI/ML chips ca... » read more

← Older posts