tag: area

Power/Performance Costs In Chip Security
By Adam Kovac - 16 May, 2024 - Comments: 0

Hackers ranging from hobbyists to corporate spies and nation states are continually poking and prodding for weaknesses in data centers, cars, personal computers, and every other electronic device, resulting in a growing effort to build security into chips and electronic systems. The current estimate is that 60% of chips and systems have some type of security built in, and that percentage is ... » read more

Placement And CTS Techniques For High-Performance Computing Designs
By Siemens EDA - 09 Nov, 2023 - Comments: 0

This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

HBM3 In The Data Center
By Ed Sperling - 17 Oct, 2022 - Comments: 0

Frank Ferro, senior director of product management at Rambus, talks about the forthcoming HBM3 standard, why this is so essential for AI chips and where the bottlenecks are today, what kinds of challenges are involved in working with this memory, and what impact chiplets and near-memory compute will have on HBM and bandwidth.     » read more

Can Analog Make A Comeback?
By Brian Bailey - 09 Jun, 2022 - Comments: 3

We live in an analog world dominated by digital processing, but that could change. Domain specificity, and the desire for greater levels of optimization, may provide analog compute with some significant advantages — and the possibility of a comeback. For the last four decades, the advantages of digital scaling and flexibility have pushed the dividing line between analog and digital closer ... » read more

Wrestling With Analog At 3nm
By Brian Bailey - 09 Sep, 2021 - Comments: 0

Analog engineers are facing big challenges at 3nm, forcing them to come up with creative solutions to a widening set of issues at each new process node. Still, these problems must be addressed, because no digital chip will work without at least some analog circuitry. As fabrication technologies shrink, digital logic improves in some combination of power, performance, and area. The process te... » read more

Creating Domain-Specific Processors Using Custom RISC-V ISA Instructions
By Codasip - 23 Sep, 2020 - Comments: 0

When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores responsible for varied functions such as running the main application programs, communications, signal processing, security, and managing storage. Traditionally, such cores have been in distinct categor... » read more

Ensuring Functional Safety In Design
By Ed Sperling - 05 Feb, 2020 - Comments: 0

Mohammed Abdelwahid (Ali), automotive logic test product manager at Mentor, a Siemens Business, discusses how to maximize coverage in the different ASIL standards for logic BiST, how to make testing more efficient, and what impact that has on area and test time. » read more

Tradeoffs In Embedded Vision SoCs
By Ed Sperling - 28 Jan, 2020 - Comments: 0

Gordon Cooper, product marketing manager for embedded vision processors at Synopsys, talks with Semiconductor Engineering about the need for more performance in these devices, how that impacts power, and what can be done to optimize both prior to manufacturing. » read more

Using Compression For High-Bandwidth Video
By Ed Sperling - 01 Aug, 2019 - Comments: 0

Malte Doerper, senior manager for product management at Synopsys, explains how to improve bandwidth and reduce latency in video without changing out the existing infrastructure through compression, but unlike previous versions of compression there is no significant loss of quality. This approach reduces power, area and heat, as well. » read more

Complexity’s Impact On Security
By Ed Sperling - 01 May, 2019 - Comments: 0

Ben Levine, senior director of product management for Rambus’ Security Division, explains why security now depends on the growing number of components and the impact of interactions between those components. This is particularly problematic with AI chips, both on the training and inferencing side, where security problems on the training side can alter models for AI inferencing. » read more

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