tag: ARM

Tradeoffs To Improve Performance, Lower Power
By Ann Mutschler - 11 Mar, 2021 - Comments: 0

Generic chips are no longer acceptable in competitive markets, and the trend is growing as designs become increasingly heterogeneous and targeted to specific workloads and applications. From the edge to the cloud, including everything from vehicles, smartphones, to commercial and industrial machinery, the trend increasingly is on maximizing performance using the least amount of energy. This ... » read more

MRAM Evolves In Multiple Directions
By Bryon Moyer - 11 Mar, 2021 - Comments: 1

Magnetoresistive RAM (MRAM) is one of several new non-volatile memory technologies targeting broad commercial availability, but designing MRAM into chips and systems isn't as simple as adding other types of memory. MRAM isn’t an all-things-for-all-applications technology. It needs to be tuned for its intended purpose. MRAMs targeting flash will not do as well targeting SRAMs, and vice vers... » read more

Blog Review: March 10
By Jesse Allen - 10 Mar, 2021 - Comments: 0

Siemens EDA's Harry Foster checks out how the maturity of verification processes impact bug escapes in FPGA designs and whether safety critical development processes prevent bugs from escaping to silicon. Synopsys' Dennis Kengo Oka examines the weaknesses and vulnerabilities in automotive keyless entry systems and how security researchers hacked the Tesla Model X key fob. Cadence's Paul M... » read more

A Layered Approach To High Performance Device Virtualization
By Arm - 10 Mar, 2021 - Comments: 0

The complexity and performance requirements of computing systems have been growing and demands are further driven by applications, such as ML and the everything-connected world of IoT with many billions of connected devices. Arm has developed a virtualization and accelerator strategy to address this, which we discuss in this white paper from our Architecture and Technology Group A layered... » read more

Blog Review: March 3
By Jesse Allen - 03 Mar, 2021 - Comments: 0

Siemens EDA's Ray Salemi considers incrementalism in engineering, the transition from drawing circuits to writing RTL, and the next big leap of using proxy-driven testbenches written in Python. Cadence's Shyam Sharma looks at key changes from LPDDR5 in the LPDDR5X SDRAM standard, which extends clock frequencies to include 937MHz and 1066MHz resulting in max data rates of 7500MT/s and 8533 MT... » read more

Chiplets For The Masses
By Brian Bailey - 03 Mar, 2021 - Comments: 2

Chiplets are a compelling technology, but so far they are available only to a select few players in the industry. That's changing, and the industry has taken little steps to get there, but timing for when you will be able to buy a chiplet to integrate into your system remains uncertain. While new fabrication nodes continue to be developed, scaling is coming to an end, be it for physical or e... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Feb, 2021 - Comments: 0

Cadence completed the acquisition of NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. Founded in 1993 as a spin-off of the Vrije Universiteit Brussel (VUB), NUMECA was based in Brussels, Belgium. Terms of the deal were not disclosed... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 26 Feb, 2021 - Comments: 0

Automotive/Mobility Toyota Motor Corporation developed a hydrogen fuel cell (FC) system packaged in a compact module. Toyota plans to start selling it in the spring of 2021. The module can be used by other companies developing products powered by fuel cells. Micron is sampling an ASIL D level LPDDR5. The low-power memory is qualified for automotive safety applications. Samsung Foundry ce... » read more

Firmware Skills Shortage
By Brian Bailey - 25 Feb, 2021 - Comments: 0

Good hardware without good software is a waste of silicon, but with so many new processors and accelerator architectures being created, and so many new skills required, companies are finding it hard to hire enough engineers with low-level software expertise to satisfy the demand. Writing compilers, mappers and optimization software does not have the same level of pizazz as developing new AI ... » read more

Blog Review: Feb. 24
By Jesse Allen - 24 Feb, 2021 - Comments: 0

Siemens EDA's Harry Foster checks out the efficiency and effectiveness of verification on ASIC and IC designs with a look at how many projects meet the original schedule, the number of required spins, and classification of functional bugs. Cadence's Paul McLellan listens in as Philippe Magarshack of ST Microelectronics on how the company uses massive amounts of data generated by its fabs to ... » read more

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