Week In Review: Design, Low Power

Cadence finalizes CFD acquisition; Applied Materials buys DTCO company; emulation for HW-SW power; fast tracking RISC-V extensions.


Cadence completed the acquisition of NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. Founded in 1993 as a spin-off of the Vrije Universiteit Brussel (VUB), NUMECA was based in Brussels, Belgium. Terms of the deal were not disclosed.

“With the addition of NUMECA’s technology to the Cadence portfolio, we are broadening our system analysis capabilities and integrated design solutions, addressing critical customer challenges in areas such as internal and external flows, acoustics, heat transfer, fluid-structure interaction and optimization,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence.

Applied Materials acquired Sage Design Automation. Sage provides Design-Technology Co-Optimization (DTCO) tools for both logic and memory to explore combinations of different materials, process and transistor device configurations for analysis of their interdependencies and PPAC trade-offs at a design and system level. Its integrated design rule management technology combines graphical design rule capture with the ability to generate correct-by-construction checks. Sage is based in Santa Clara, Calif.

Tools & IP
Synopsys debuted ZeBu Empower, an emulation system for hardware-software power verification of multi-billion gate SoC designs. The system allows software and hardware designers to utilize power profiles to identify substantial power improvement opportunities for dynamic and leakage power. It also feeds forward power-critical blocks and time windows into Synopsys’ PrimePower engine for RTL power analysis and gate-level power sign-off. AMD and SiM.ai noted using ZeBu Empower.

Ansys announced Moxie, a product to run and analyze SysML behavioral models in virtual environments and confirm these designs represent systems that will satisfy mission performance requirements for applications such as aerospace, satellites, and automotive. It integrates SysML authoring tools with mission modeling tools such as AGI’s Systems Tool Kit and provides continuous event detection during simulation runs, synchronizes execution of multiple simulation technologies, and allows customizable levels of simulation fidelity. Defense company Parsons noted using the tool.

RISC-V International unveiled its Fast Track Architecture Extension Process (Fast Track) targeted at streamlining the ratification of small architecture extensions. Fast Track is designed for extensions that are simple, uncontentious, offer value to a large portion of the RISC-V community, and cleanly fit into existing RISC-V architecture. Once an extension has been submitted for consideration it will undergo an internal review before entering a 45-day public review process.

ZiHintPause, the first extension to be ratified under this new process, enables engineers to reduce the energy consumption of their designs. The extension also helps improve the performance of spin-wait loops and enable multithreaded cores to temporarily relinquish extension resources. The ZiHintPause extension adds a single PAUSE instruction (encoded as a HINT instruction) to the ISA.

Xilinx announced a range of new data center products and solutions, including a new family of Alveo SmartNICs, smart world AI video analytics applications, an accelerated algorithmic trading reference design for sub-microsecond trading, and the Xilinx App Store. The Alveo products are composable SmartNICs offering software-defined hardware acceleration for all function offloads. SN1000 SmartNICs directly offload CPU intensive tasks to optimize networking performance and can accelerate a broad range of network functions at line rate.

Samsung Foundry certified Synopsys’ IC Validator physical verification solution for its 5nm and 4nm process technologies. IC Validator includes fast DRC checking, programmable electrical rule checks, dummy metal fill, and design-for-manufacturability enhancement capabilities, and signoff accurate StarRC integration.

CEVA uncorked a highly-integrated wireless audio platform for Bluetooth audio devices. The Bluebud platform aims to provide a standardized and self-contained solution that can be dropped into an SoC design. It contains CEVA’s RivieraWaves Bluetooth 5.2 IP, with both Classic Audio and LE Audio, and the CEVA-BX1 audio processor, together with all the required peripherals for wireless audio, in a low power design with a footprint of less than 0.5mm2 in 22nm.

IAR Systems’ C/C++ development toolchain IAR Embedded Workbench for Arm now supports 64-bit Arm cores including Arm Cortex-A35, Cortex-A53 and Cortex-A55. It provides debugging and analysis possibilities such as complex code and data breakpoints, runtime stack analysis, call stack visualization, code coverage analysis and integrated monitoring of power consumption.

Nanjing Tianyihexin Electronics selected Codasip’s L30 (originally Bk3) RISC‑V‑based core for their True Wireless Stereo (TWS) headset and intelligent wearable devices solutions. The processor will be integrated into the Hx9131 product, which provides multi-point, high-precision capacitive sensing for contact and non-contact multi-touch and gesture recognition. Codasip L30 will provide control functions to the overall system, including sliding, double-clicking, long-press, and other operations to create a comfortable control experience for customers using the TWS headset.

Rambus and Andes Technology are teaming up on a complete low-power, size-optimized secure solution for MCUs and IoT applications. The effort will integrate Andes RISC-V -based CPUs with Rambus Security Root of Trust, which can boot the MCU, protect the device identity and offers authentication, secure debug, and other cryptographic services to the host system.

Rambus also extended its patent license agreement with AMD, allowing AMD to continue to be licensed for its products. This is the two companies’ fourth continuous agreement.

Ansys and Keysight Technologies are collaborating to integrate component-level designs into mission modeling environments with an enhanced, automated DME workflow. The automated workflow directly connects AGI’s multi-domain mission analysis software with Keysight’s high-fidelity RF systems modeling tool to combine mission-level modeling with component-level system design throughout the product lifecycle.

Ansys Mechanical was integrated with Optimo Medical AG’s Optimeyes digital twin technology to enable ophthalmologists to create identical digital copies of patient corneas to test surgical strategies for individual patients and run in silico clinical trials of new eye products.

Numbers & People
Cadence reported fourth quarter and fiscal year 2020 financial results. Revenue for Q4 2020 was $760 million, up 26.7% from the same quarter last year. On a GAAP basis, operating margin was 24% and earnings were $0.62 per share for the quarter, down 73.7% from $2.36 per share for Q4 2019. In Q4 2020, non-GAAP operating margin was 35% with earnings per share of $0.83, up 53.7% from $0.54 per share in the prior Q4.

For the full year, revenue was $2.68 billion, up 14.9% from 2019’s revenue. On a GAAP basis, operating margin was 24% and earnings were $2.11 per share for 2020, down 40.2% from $3.53 the year before.  Non-GAAP operating margin was 35% with earnings of $2.80 per share, up 27.3% from $2.20 per share in 2019.

The company noted that GAAP net income for the fourth quarter of 2019 and fiscal 2019 included a one-time non-cash tax benefit of $576 million related to intercompany transfers of certain intellectual property rights to Cadence’s Irish subsidiary.

Matthew Ballance is the recipient of the 2021 Accellera Technical Excellence Award. A member of the Portable Stimulus Working Group and a Product Engineer and Portable Stimulus Technologist with Siemens Digital Industries Software, Ballance drove developments of PSS 2.0 by leading the sub-working group defining semantics of core language features, as well as being heavily involved in three additional PSS sub-working groups.

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The International Symposium on Field-Programmable Gate Arrays will take place Feb. 28-Mar. 2.

In March, DVCon 2021 will be held Mar. 1-4. The U.S. government-focused electronics conference GOMACTech will be held Mar. 29-Apr. 1.

DAC changed dates to Dec. 5-9 and plans to hold an in-person conference in San Francisco, Calif. It will be co-located with SEMICON West, which will take place Dec. 7-9.

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