Focus More Attention On The SoC’s Central Nervous System


In multiple conversations over the years, I’ve often compared the interconnect fabric within SoC designs to the central nervous system of the human body. The point that I try to make is that the potential of the SoC’s performance and functionality is tied to the information that travels through the fabric and interconnect to all the on-chip IP components. Improving a chip’s ability to com... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions Silvaco acquired Invarian, anticipating integration of Invarian's methodology will accelerate adoption of concurrent power-voltage-thermal analysis. Legal A U.S. District Court judge ordered Kilopass to pay $5.5 million to Sidense for legal fees incurred in Kilopass' patent infringement suit against Sidense. That lawsuit was  dismissed in 2012. Sidense filed... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions NXP acquired Quintic’s Bluetooth Low Energy and Wearable businesses, adding BLTE to their low power RF-connectivity portfolio. The team of approximately 65 is expected to join NXP when the deal closes in Q1 2015. Tools Cadence unveiled the integration of Forte's Cynthesizer with their own C-to-Silicon Compiler. The result is the Stratus high-level synthesis... » read more

Partition Lines Growing Fuzzy


For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

Custom Versus Platform Design


The increase in [getkc id="81" kc_name="SoC"] complexity is being mirrored by a rise in complexity within the markets that drive demand for those chips. The upshot is that a push toward greater connectivity, lower power and better performance—and all for a minimal cost—has turned the pros and cons for custom design vs. platforms and superchips into a murky decision-making process. For t... » read more

Streamlining Interconnect Integration Accelerates Globally Distributed Design


As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on a particular aspect of the SoC, the hard part comes in integrating these individual design efforts together. When something goes wrong and it doesn’t work, the compan... » read more

The Week In Review: Design/IoT


Deals Arteris teamed up with Yogitech to integrate the two companies' products. They're planning a set of ISO 26262 deliverables for a series of SoC reference designs and a functional safety assessment of the Arteris FlexNoC interconnect IP. ARM and Green Hills Software collaborated on an optimized compiler for the Cortex-R5 processor. The compiler achieved a score of 1.01EEMBC Automarks/... » read more

Challenges For IC Security


Keeping chips secure is really a foot race between the good guys and the bad guys. Going forward, expect heavily funded, grouped efforts to place tremendous pressure on security envelopes. This includes everything from simple home devices, such as routers, to the most critical infrastructures, such as power, telecom, transportation, and soon, the IoT. Fig. 1: Courtesy of Blade Genexis I... » read more

Back To The Future


The push to the next process node typically has meant that designs get simpler at existing and older nodes because the process technology is more mature and there have been so many chips developed at those nodes—many billions of them—that every possible corner case has been encountered hundreds, if not thousands, of times. That all makes sense in theory, but several key things have chang... » read more

First Look: 10nm


As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

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