tag: Arteris

The Week In Review: Design
By Ann Mutschler - 11 Apr, 2014 - Comments: 0

Tools Mentor Graphics announced its Enterprise Verification Platform (EVP) that pulls together the company’s Questa verification technologies with Veloce OS3 global emulation resourcing technology, and the Visualizer debug technology into what it says is a globally accessible, high-performance datacenter resource. The system is aimed at global resource management and supports project teams a... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Malaysia Airlines Flight MH370 And The Progress of Technology
By Kurt Shuler - 31 Mar, 2014 - Comments: 1

Cable news has been continuously deluging us with lots of speculation regarding the fate of Malaysia Airlines flight 370. Most of us are drowning in a sea of jargon as TV talking heads express incredulity that, “with all our modern technology, a plane disappeared…” Although the disappearance of flight MH370 is a terrible tragedy, I see the larger context of our progress in commercial a... » read more

New Approaches For Reliability
By Ed Sperling - 28 Mar, 2014 - Comments: 0

The definition of reliability hasn’t budged since the invention of the IC, but how to achieve it is starting to change. In safety-critical systems, as well as in markets such as aerospace, demands for reliability are so rigorous that they often require redundant circuitry—and for good reason. A PanAmSat malfunction in 1998 caused by tin whisker growth wiped out pagers for 45 million use... » read more

How Much Will That Chip Cost?
By Ed Sperling - 27 Mar, 2014 - Comments: 1

From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those proce... » read more

Blog Review: March 12
By Ed Sperling - 12 Mar, 2014 - Comments: 0

Arteris’ Kurt Shuler is sounding the alarm bell for the semiconductor industry. He observes that system OEMs are hiring their own chip engineers. Well, that should wake up someone. Danger Will Robinson. Mentor’s Colin Walls points to a festering debate in the embedded software world about priorities and openness to learning new tools and approaches. Embedded software developers are a rat... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

Blog Review: March 5
By Ed Sperling - 05 Mar, 2014 - Comments: 0

ARM’s Lori Kate Smith has discovered an unusual electronic billboard advertisement for shampoo on a train platform in Sweden. Watch what happens when the train goes by. Mentor’s J. VanDomelen puts a magnifying glass on the U.S. Defense budget and where the money is going. Times have changed with technology. Who needs soldiers? Cadence’s Brian Fuller interviews Mindtree CTO S. Janaki... » read more

Abstractions: The Good, Bad And Ugly
By Ed Sperling - 27 Feb, 2014 - Comments: 0

Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Time to mend the EE / CS divide
By Kurt Shuler - 27 Feb, 2014 - Comments: 0

There’s been a lot of news out the last few weeks about the future of our industry, and although these news flashes may seem unrelated, they are quite correlated. First, there was the disturbing news in Mark LaPedus’ article here on Semiconductor Engineering, “EUV Suffers New Setback,” portending a rough ride for the commercialization of EUV lithography. EUV will be needed to create ... » read more

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