tag: Arteris

Where Do We Stand With CDC?
By Ann Mutschler - 26 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: While not a new aspect of design, clock domain crossing is... » read more

3 Challenges Of Delivering Configurable Semiconductor IP
By Kurt Shuler - 26 Jun, 2014 - Comments: 0

Over time, commercial IP products have morphed from single function blocks to 100% configurable IPs where no two instances are the same. In this article I point out the challenges of creating configurable IP, and the best-known practices to address them. IP Configurability Spectrum Throughout the history of chip design, there has been a spectrum of configurability that has been built into i... » read more

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Executive Insight: Charles Janac
By Ed Sperling - 30 May, 2014 - Comments: 0

SE: What’s your biggest concern? Janac: Staying current. One of the things that is really important is to understand shifts in the marketplace. In the past, we looked at whether to target our interconnect solution at digital TV or mobility. This was actually a very interesting question in 2005. The DTV market looked better, but we were not getting enough evaluations. We were doing better i... » read more

New Business Model: Flexible Silos
By Ed Sperling - 22 May, 2014 - Comments: 0

Operational silos within organizations have a long history of streamlining processes and maximize efficiency. In fact, that approach has made enterprise resource planning applications a must-have for most companies, and cemented the fortunes of giants such as SAP and Oracle, as well as the giant consulting companies that recommend them. But those kinds of delineations don’t work so well fo... » read more

Efficiency Metrics Get Fuzzy
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Not too long ago chipmakers used to measure transistors per hour and software developers would measure lines of code written per day or per week. Those metrics have fallen by the wayside—and chipmakers are still lamenting that loss. The problem is that nothing has come along to replace the old metrics, and complexity has left many chipmakers scratching their heads about how to build effici... » read more

SoC Assembly And IP Reuse
By Kurt Shuler - 24 Apr, 2014 - Comments: 2

I had the honor and opportunity to present at the 2014 Electronic Design Process Symposium in Monterey last Friday. This annual workshop is run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. There were more than 30 participants each day. Most of them very experienced people with lots of technical and business responsibilities. It was ... » read more

The Week In Review: Design
By Ann Mutschler - 11 Apr, 2014 - Comments: 0

Tools Mentor Graphics announced its Enterprise Verification Platform (EVP) that pulls together the company’s Questa verification technologies with Veloce OS3 global emulation resourcing technology, and the Visualizer debug technology into what it says is a globally accessible, high-performance datacenter resource. The system is aimed at global resource management and supports project teams a... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Malaysia Airlines Flight MH370 And The Progress of Technology
By Kurt Shuler - 31 Mar, 2014 - Comments: 1

Cable news has been continuously deluging us with lots of speculation regarding the fate of Malaysia Airlines flight 370. Most of us are drowning in a sea of jargon as TV talking heads express incredulity that, “with all our modern technology, a plane disappeared…” Although the disappearance of flight MH370 is a terrible tragedy, I see the larger context of our progress in commercial a... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy