The Interconnect Game

By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling Having a single bus protocol is something most SoC engineers can only dream about. Reality is often a jumble of protocols determined by the IP they use, which can slow down a design’s progress. The problem stems largely from re-use and legacy IP. While it might be convenient to use only on an AXI standard protocol from ARM, most chips are a combination of IP tied to specif... » read more

Server Processor War Heats Up

By Kurt Shuler - 26 Apr, 2012 - Comments: 0

By Kurt Shuler Yesterday’s announcement that Intel will acquire Cray’s interconnect hardware program, including IP and 74 employees, is the latest salvo in the race to develop commercially viable massively multicore server processors. On the surface, this acquisition seems like another instance of Intel beefing up its board-level interconnect technology, after having already acquired Fu... » read more

Roundtable: Bridging Hardware And Software

By Ed Sperling - 25 Apr, 2012 - Comments: 0

System-Level Design talks about where the problems are with hardware-software co-design and how much progress we've made with Narendra Konda of Nvidia, Frank Schirrmeister of Cadence, Shabtay Matalon of Mentor Graphics, Kurt Shuler of Arteris and Jack Greenbaum of Green HIlls Software. [youtube vid=EOUPsDOYGq8] » read more

Power Benefits Of Modular Interconnect Design Using Network-On-Chip Technology

By Various Writers - 25 Apr, 2012 - Comments: 0

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units. This... » read more

Experts At The Table: Designing At 28nm And Beyond

By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and... » read more

Experts At The Table: Designing At 28nm And Beyond

By Ed Sperling - 30 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), an... » read more

Experts At The Table: Designing At 28nm And Beyond

By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), an... » read more

Coherency Becomes A Stack Of Issues

By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

The Three Consequences Of Fewer Design Starts

By Kurt Shuler - 22 Mar, 2012 - Comments: 0

By Kurt Shuler Gartner’s Feb. 27 report, “Market Trends: Worldwide, ASIC and ASSP Design Starts Continue Declining Trend, 2012,” by analysts Bryan Lewis and Ganesh Ramamoorthy, gives all of us insight into what the semiconductor world will look like a few years in the future. Combined with Gartner’s reports on semiconductor design IP, we can gain an understanding of how the semicond... » read more

New Winners And Losers

By Ed Sperling - 22 Mar, 2012 - Comments: 0

The realignment of the semiconductor industry has begun, most of it beneath the radar screen. In a disaggregated supply chain, any piece in isolation looks insignificant. But taken together, these shifts begin to paint a picture of a broad realignment and refocusing of the entire industry that ultimately will cement the fortunes of some and create new winners and losers out of others. The fi... » read more

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tag: Arteris

The Interconnect Game

Server Processor War Heats Up

Roundtable: Bridging Hardware And Software

Power Benefits Of Modular Interconnect Design Using Network-On-Chip Technology

Experts At The Table: Designing At 28nm And Beyond

Experts At The Table: Designing At 28nm And Beyond

Experts At The Table: Designing At 28nm And Beyond

Coherency Becomes A Stack Of Issues

The Three Consequences Of Fewer Design Starts

New Winners And Losers