Embedded FPGA Timing

By Ed Sperling - 03 Aug, 2018 - Comments: 0

Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. https://youtu.be/Jq4XUKnniB4 » read more

High-Speed SerDes At 7nm

By Ed Sperling - 30 Jul, 2018 - Comments: 0

eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power. https://youtu.be/E-CU8TLvjjc » read more

Pros, Cons Of ML-Specific Chips

By Ed Sperling - 27 Jul, 2018 - Comments: 1

Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation. To view part one, click here. Part two is here. SE: Is the industry's knowledge of machine learning keeping up with th... » read more

Moving To ASICs For ADAS

By Gary Dagastine - 19 Jul, 2018 - Comments: 0

By some estimates, there are now more than 260 startups and established companies around the world scrambling to develop, qualify and bring to market chips and technologies for new ADAS (advanced driver-assistance systems) and autonomous driving applications. Accordingly, venture capitalists, technology companies, carmakers, Tier 1 automotive suppliers and others are sharply ratcheting up ... » read more

Challenges At The Edge

By Kevin Fogarty - 03 May, 2018 - Comments: 0

By Kevin Fogarty and Ed Sperling Edge computing is inching toward the mainstream as the tech industry begins grappling with the fact that far too much data will be generated by sensors to send everything back to the cloud for processing. The initial idea behind the IoT/IIoT, as well as other connected devices, was that simple sensors would relay raw data to the cloud for processing throug... » read more

Resets And Reset Domain Crossings In ASIC And FPGA Designs

By Aldec - 25 Apr, 2018 - Comments: 0

This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To download this paper, clic... » read more

AI: The Next Big Thing

By Ed Sperling - 15 Mar, 2018 - Comments: 2

The next big thing isn't actually a thing. It's a set of finely tuned statistical models. But developing, optimizing and utilizing those models, which collectively fit under the umbrella of artificial intelligence, will require some of the most advanced semiconductors ever developed. The demand for artificial intelligence is almost ubiquitous. As with all "next big things," it is a horizonta... » read more

Tech Talk: On-Chip Variation

By Ed Sperling - 01 Mar, 2018 - Comments: 0

Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more

Deconstructing Deep Learning

By Mike Gianfagna - 22 Feb, 2018 - Comments: 0

I discuss AI and deep learning a lot these days. The discussion usually comes back to “what is a deep learning chip?” These devices are basically hardware implementations of neural networks. While neural nets have been around for a while, what’s new is the performance advanced semiconductor technology brings to the party. Applications that function in real time are now possible. But wh... » read more

eSilicon Builds ASIC Business On Leading-Edge Chip Design

By eSilicon - 21 Feb, 2018 - Comments: 0

How advanced application specific integrated circuits (ASIC) chip design and manufacturing for leading-edge applications such as networking and artificial intelligence can be successfully outsourced. The company which has capabilities in 2.5D packaging, high-bandwidth memories (HBM), and silicon IP for fast memories and SerDes designs. The company has many leading system companies as custome... » read more

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tag: ASICs

Embedded FPGA Timing

High-Speed SerDes At 7nm

Pros, Cons Of ML-Specific Chips

Moving To ASICs For ADAS

Challenges At The Edge

Resets And Reset Domain Crossings In ASIC And FPGA Designs

AI: The Next Big Thing

Tech Talk: On-Chip Variation

Deconstructing Deep Learning

eSilicon Builds ASIC Business On Leading-Edge Chip Design

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