FPGA Verification with Assertions: Why Bother?


This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions. To download this white paper, click here. » read more

The Controversial Spec


By Ann Steffora Mutschler Design sophistication and complexity has made it increasingly difficult to fully specify the expected behavior of a block in an SoC, but this is necessary for design and verification teams. How do you write a “good” and “complete” specification of functionality? It turns out that the discussion of defining what a good and complete specification is and how t... » read more

Formal Verification Comes Of Age


By Ann Steffora Mutschler Formal verification technology, also known as formal property checking, has been in existence since the early 1990s. Still, it’s only in the past five years that it has made big strides in the last five years in terms of the capacity of the technology to handle bigger pieces of a design, leveraging advancements in computing as well as improvements to the algor... » read more

A Necessary Duo: IP And Assertions


By Ann Steffora Mutschler Assertions are key to complete and accurate verification, as I dove into here, and there are implications for IP as well. In the case of an embedded processor core that is shipped out as an RTL by the IP vendor, and then used by an engineering team to create a cell phone SoC or to create a consumer SoC for a set-top box or what have you, that core goes into an end ... » read more

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