Interconnect Challenges Grow

By Mark LaPedus - 20 Feb, 2014 - Comments: 0

Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

What’s After 3D NAND?

By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus Planar NAND flash memory is on its last scaling legs, with 3D NAND set to become the successor to the ubiquitous 2D technology. Samsung Electronics, for one, already has begun shipping the industry’s first 3D NAND device, a 24-level, 128-gigabit chip. In addition, Micron and SK Hynix shortly will ship their respective 3D NAND devices. But the Toshiba-SanDisk duo are the lo... » read more

Getting Ready For High-Mobility FinFETs

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node. Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts t... » read more

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tag: atomic-level deposition

Interconnect Challenges Grow

What’s After 3D NAND?

Getting Ready For High-Mobility FinFETs