Getting Ready For High-Mobility FinFETs

New materials, approaches and structures compete over cost, ease of use; lots of possible combinations emerge.


By Mark LaPedus
The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node.

Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts to introduce their initial finFET processes at 14nm. And the foundries are already defining their next-generation finFETs at 10nm.

Chipmakers face numerous challenges in terms of ramping up their first- and next-generation finFETs. But the challenges, and costs, could pale in comparison when vendors extend finFET technology to the 7nm and 5nm nodes—or perhaps beyond.

Starting at 7nm, chipmakers plan to inject finFETs with various and exotic III-V materials in the channels to boost the mobility, which refers to how fast the electrons can move through a device. Currently, the industry has narrowed the options down to about five leading candidates for the high-mobility finFET era: finFETs with germanium (Ge) for the PFET; finFETs with Ge for both PFET and NFET; and finFETs with Ge for PFET and III-V materials for NFET.

The two possible spoilers are tunnel field-effect transistors (TFETs) and nanowire-based gate-all-around finFETs. “Conventional thinking currently suggests that we will see a Ge PFET and an InGaAs NFET at 7nm,” said Dean Freeman, an analyst with Gartner. “If the industry could make a silicon nanowire, and create a transistor using silicon and high-k/metal-gate, then we could see the industry move in that direction.”

The III-V materials themselves exist today, but many of the associated manufacturing techniques are in their infancy or simply don’t exist. Bringing up compound semiconductor materials in silicon fabs is a monumental task. And the ability to design and integrate III-V finFETs in a cost-effective manner is easier said than done. “This is not a straightforward process,” said Luc Van den hove, chief executive of IMEC. “We are talking about materials with different lattice constants.”

The challenges leave some observers wondering whether chipmakers should skip the high-mobility finFET era and move directly to the more exotic technologies like carbon nanotubes and graphene. Perhaps the best avenue is the pursuit of stacked 2.5D/3D devices.

Looking into his crystal ball, Gary Patton, vice president of IBM’s Semiconductor Research and Development Center, predicts the two 3D-like approaches, finFETs and stacked die, will have a long and viable future. “The 3D era should carry us well into the 2020 timeframe,” Patton said. “I expect finFETs will last a decade. But then at some point, we hit the atomic dimension limit. Then, we’re talking about silicon nanowires and carbon nanotubes. And to deal with the interconnect issues, we have to talk about integrating photonics on the chip and stacking multiple chips together. That’s really in the next decade.”

Take III-V
Today, the industry is moving towards an inflexion point. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects. So, at 14nm, foundries will introduce finFETs, which have better short-channel electrostatic characteristics than planar.

Today’s finFETs will likely scale at least two generations to 10nm, said Subramani Kengeri, vice present of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V materials to provide a mobility boost, Kengeri said.

The next roadblock is that today’s strained-silicon technology is under stress. For some time, chipmakers have used a silicon-germanium (SiGe) alloy stressor in the channel to boost carrier mobility. “Starting from the 90nm and 65nm nodes, the source-drain areas have been grown using a SiGe epi process in order to bring strain into the device,” said IMEC’s Van den hove. “With strain, we can increase the drive current and device mobility. In the finFET structure, we can do that as well. But this space is very limited, because of the [difficulties] to introduce enough strain into those tiny channels. An alternative way to boost the drive current is by using materials that have intrinsically higher mobilities. This will reduce power consumption.”

The first of these high-mobility devices is expected to appear at 7nm, with the emergence of a finFET with Ge in the p channel and tensile silicon in the n channel. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,400cm-square-over-Vs for silicon.

“But germanium in the p channel is not a straightforward process,” said Aaron Thean, director of the logic program at IMEC. “Germanium tends to move around once exposed to temperature. So the challenges are defects and the structural stability of the device. The surface passivation (for the high-k/metal-gate stack) is also very tricky.”

Following this device, the industry will move to a next-generation high-mobility finFET at 7nm. The first option is a finFET with Ge for both the p and n channels. The second option is Ge for the p channel and indium gallium arsenide (InGaAs) for the n channel. InGaAs has an electron mobility of 12,000cm-square-over-Vs.

“Those two options are competing,” Thean said. “The germanium-germanium option requires compressively strained Ge in the p channel and relaxed Ge in n channel. There are issues with the gate stack and dopant activation.”

Intel and others are leaning toward the Ge-InGaAs option. “InGaAs is our front-up option. It can offer mobilities up to 10X and higher. It’s a better-understood III-V material. I wouldn’t say InGaAs is easy in terms of processing, but it is not as challenging of a material to handle,” Thean said.

The other 7nm candidate is the gate-all-around (GAA) finFET, which can have two or more gates that are wrapped around by a nanowire channel. Purdue University, for one, recently demonstrated GAA finFET with 20nm channel lengths and a sub-threshold swing of 63mV/decade. “There are still lots of challenges with GAA,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “We still need to address the source/drain contact issue. The surface roughness needs to be improved and the variability issues need further study.”

Intel and others also have shown interest in the TFET, which may appear at 5nm. In TFET, a tunnel barrier is created at the source-channel contact to increase the drive currents. Using III-V materials, the TFET promises to scale the supply voltage beyond 0.5 volts, said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “TFETs enable steeper sub-threshold voltages,” he said.

There are other options, such as exotic III-V materials for both NFET and PFET. Other III-V materials, including indium antimonide (InSb), are still in R&D. The Sb materials are promising, but have narrow band gaps.

Tool gaps
All of the futuristic, high-mobility finFET devices suffer from the same problem—they are expensive and difficult to manufacture. The most obvious problem is lithography. It’s still unclear if extreme ultraviolet (EUV) lithography will be ready for the 7nm node, meaning the industry may need to extend 193nm immersion and multiple patterning.

Patterning is only one piece of the finFET puzzle. “Lithography has been the story for at least the last 10 years,” said Mike Splinter, chairman and chief executive of Applied Materials. “Now, we are seeing many of the bottlenecks in interface engineering, precision materials and how are you going to get the low-k values.”

For example, RF chipmakers have been fabricating III-V chips in trailing-edge fabs at smaller wafer sizes. At 7nm, the challenge is to grow III-V materials on 300mm or 450mm silicon wafers with good yields and throughput.

It’s unclear which technology, bulk or FD-SOI, will prevail at 7nm and beyond. STMicroelectronics says FD-SOI can extend to at least 10nm and perhaps beyond. “We are continuing to look at SOI,” said IMEC’s Thean. “The nice thing about fully-depleted devices on SOI is that they have excellent isolation.”

In one emerging SOI effort, Ed Nowak, device chief designer at IBM, recently described a fin-on-oxide (Fox) technology that could scale to 5nm. Fox enables a finFET technology with oxide dielectric isolation. Like SOI, Fox enables the finFET manufacturer to produce a controlled fin height, thereby reducing variability. Silicon wafer maker MEMC recently rolled out SOI substrates based on Fox.

The integration between III-V and silicon is perhaps the biggest issue. “In III-V, for example, we use gold as a contact material,” said Raj Jammy, vice president of emerging technologies at Sematech. “Gold is a poisonous material for silicon. So, you need to come up with a new contact metal scheme.”

There is also a need for new metrology tools to find defects in III-V finFETs. New tools are also are required for GAA finFETs with nanowires. “When it comes to gate all-around, you need selective ALD processes,” Jammy said. “For fin/gate fidelity, this requires selective III-V/Ge epi. For etch, we might not be able to use the processes we have today. We are looking into ALD etch.”

The industry is making progress on one front. “One of the areas we are looking at is a low damage conformal 3D doping technique, which we call monolayer doping,” he said. “This enables selective and very shallow junctions. We have solutions with arsenic and phosphorous. What is exciting about this is that the fins that have monolayer doping don’t have any damage.”

All told, high-mobility finFETs promise to enable chip scaling, but the challenges and costs are steep. “There is no free lunch,” he added.

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