tag: ATPG

Addressing Test Cost Challenges In LPCT Designs
By Cadence - 04 Aug, 2014 - Comments: 0

As companies strive to achieve higher quality and reliability for their products, and as package sizes and the number of available pins continue to shrink, there is also a persistent need to keep test costs down. Low Pin Count Test (LPCT) is one solution that Design for Test (DFT) designers turn to, and in many cases, might be the only one available to address these conflicting requirements. ... » read more

Getting A Clearer Picture
By Geir Eide - 17 Apr, 2014 - Comments: 1

Scan test diagnosis is an established software-based methodology for localizing defects causing failures in digital semiconductor devices. Using structural test patterns (such as ATPG) and the design description, diagnosis turns failing test cycles into valuable data. Exactly how valuable this data is depends on the quality of the diagnosis results. A result that points to a small group of nets... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution
By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

Optimizing Test To Enable Diagnosis-Driven Yield Analysis
By Various Writers - 21 Feb, 2013 - Comments: 0

Using diagnosis-driven yield analysis, companies have decreased their time to yield, managed manufacturing excursions and recovered yield caused by systematic defects. Dramatic time savings and yield gains have been proven using these methods. Companies must plan ahead to take advantage of diagnosis-driven yield analysis. The planning needs to include how and what patterns to generate during AT... » read more

LP Test
By Luke Lang - 11 Oct, 2012 - Comments: 0

By Luke Lang Last month, we discussed testing a portion of a chip at a time to reduce overall power dissipation during test. However, this does not address local power dissipation hotspots that can cause excessive IR drop. These hotspots can occur in regions where many nets are switching at the same time. Typically, a chip’s power grid is designed to meet IR drop specification in the func... » read more

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