tag: ATPG

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

Analog Fault Simulation Challenges And Solutions
By Mentor, a Siemens Business - 28 Sep, 2016 - Comments: 0

The test time for digital circuit blocks in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression. These technologies have greatly reduced the number of test vectors applied by automatic test equipment (ATE) while maximizing the coverage of a wide range of defect types. But for analog c... » read more

Putting Design Back Into DFT
By Brian Bailey - 25 Aug, 2016 - Comments: 0

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy. Part one of this two part series about [getkc id="47" comment="Design for Test (DFT)"] looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This co... » read more

Accelerating Design-For-Test Pattern Simulation
By Mentor, a Siemens Business - 23 Mar, 2016 - Comments: 0

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Manufacturing Test Robustness
By Kiran Vittal - 11 Sep, 2014 - Comments: 0

The recent 6.0 earthquake near Napa California caused close to $50 million in damages to the wineries and property in the region. The San Francisco bay area is accustomed to earthquakes and hence structural engineers design buildings to bear high intensity earthquakes amongst other natural disasters. The damage to property would have been much higher if not due to the strict guidelines followed... » read more

Addressing Test Cost Challenges In LPCT Designs
By Cadence - 04 Aug, 2014 - Comments: 0

As companies strive to achieve higher quality and reliability for their products, and as package sizes and the number of available pins continue to shrink, there is also a persistent need to keep test costs down. Low Pin Count Test (LPCT) is one solution that Design for Test (DFT) designers turn to, and in many cases, might be the only one available to address these conflicting requirements. ... » read more

Getting A Clearer Picture
By Geir Eide - 17 Apr, 2014 - Comments: 1

Scan test diagnosis is an established software-based methodology for localizing defects causing failures in digital semiconductor devices. Using structural test patterns (such as ATPG) and the design description, diagnosis turns failing test cycles into valuable data. Exactly how valuable this data is depends on the quality of the diagnosis results. A result that points to a small group of nets... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution
By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

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