tag: Atrenta

More Pain In More Places
By Ed Sperling - 14 Mar, 2014 - Comments: 2

Pain is nothing new in to the semiconductor industry. In fact, the pain of getting complex designs completed on budget, and finding the bugs in those designs, has been responsible for decades of continuous growth in EDA, IP, test, packaging, and foundries. But going forward there is change afoot in every segment of the flow from architecture to design to layout to verification to manufacturi... » read more

Physical-Aware RTL Restructuring For SoC Cost Reduction
By Various Writers - 14 Mar, 2014 - Comments: 0

In modern SoC design, RTL hierarchy has to be manipulated throughout the entire design flow in order to accommodate different objectives at different stages of the design process. This becomes particularly true as more and more building blocks of the SoC are reused from previous designs. These requirements are driven by the need to: Adapt the RTL design hierarchy to create homogeneous subs... » read more

Know What To Look For
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

UPF-Friendly RTL
By Bernard Murphy - 13 Mar, 2014 - Comments: 0

On a recent customer visit, we were introduced to a new term – new to us at least – “UPF-friendly RTL”. While I hadn’t heard the term, I have been going on about the concept for some time – to the point, no doubt, of becoming terminally boring. We’ve had several customers quietly doing this for years, but now I’m starting to hear it from more customers, and from 1801 committee m... » read more

SoC Integration Mistakes
By Ed Sperling - 10 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

10 Must Knows About Virtual Prototypes
By Brian Bailey - 27 Feb, 2014 - Comments: 1

1. What is a virtual prototype? If you ask a room full of people to define ‘system’, you will get as many answers as there are people in the room. The same is true for virtual prototypes. A virtual prototype defines a model of something that is usually created by one group and used by another with some implied abstraction. It is a prototype that exists as a software model on which analysis... » read more

SoC Integration Mistakes
By Ed Sperling - 26 Feb, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

Blog Review: Feb. 19
By Ed Sperling - 19 Feb, 2014 - Comments: 0

Adding a GUI to an RTOS? It may sound counterintuitive, but Mentor’s Colin Walls looks at why and where they’re being used. Cadence’s Richard Goering infuses some humor into signal integrity, which could definitely use it, courtesy of Eric Bogatin and Henny Youngman. When was the last time you saw a signal integrity engineer rolling on the floor in hysterical laughter? Well, there’s ... » read more

Power Verification in Sochi?
By Mark Baker - 14 Feb, 2014 - Comments: 1

An estimated 3 billion viewers watched in wonder at the high tech artistry of the opening ceremonies of the $50 billion Sochi Winter Olympics. As many viewers later learned, these events are often not without glitches. The after buzz was all about the Olympic ring failure. When only four of the five snowflakes transitioned into rings, the broadcasters resorted to rehearsal footage attempting to... » read more

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