tag: Atrenta

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 04 Oct, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of ... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of I... » read more

Blog Review: Sept. 18
By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

The IC Supply Chain: The Day After Tomorrow
By Atrenta - 12 Sep, 2013 - Comments: 0

Last month, I wrote about the implications of hacking in a connected world. Judgment Day from the Terminator franchise came to mind. All that paranoia is still “out there” a bit, I admit. Let’s bring it down to a more pedestrian level in this post… Plenty has been written about the disaggregated, distributed, worldwide semiconductor supply chain. Design groups all over the world work... » read more

Analysis Of Random Resistive Faults And ATPG Effectiveness At RTL
By Various Writers - 12 Sep, 2013 - Comments: 0

The use of register transfer level (RTL) descriptions for design is now commonplace throughout the electronics industry. The wide range of flexibility in both Verilog and VHDL has provided incredible freedom so that the same function may be approached from many different directions. The resulting RTL may meet the functional requirements but fail to meet various other requirements such as optimi... » read more

New Risk Factors For SoCs
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Third-party IP is becoming increasingly important in SoC designs. It saves development time and adds unique value. It also can improve performance and lower power, because a company specializing in IP frequently can build and optimize it better than a company that builds entire chips. But there are also plenty of landmines in IP integration, and there is a growing concern abo... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

Low-Power CPUs Hitting Their Stride In The Datacenter
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Without a doubt, the cloud has and continues to change the nature of the datacenter, particularly the requirements the infrastructure has to deliver. Diane Bryant, senior vice president and general manager of the Datacenter and Connected Systems Group at Intel, noted during a Webcast last week, “The infrastructure must change in support of cloud-based services.�... » read more

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