tag: Atrenta

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

Under One Roof
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Microsoft’s decision to buy Nokia’s phone business, Apple’s move to build its own chips to more effectively run its software, and Google’s effort to develop its own hardware for next-generation platforms such as Google Glass mark an interesting reversal in the electronics industry. Disaggregation was the answer to slow-moving giants such as big-iron companies. Startin... » read more

Chips And EDA: The Day After Tomorrow
By Atrenta - 08 Aug, 2013 - Comments: 0

By Mike Gianfagna Summer blockbuster movie season is in full swing, and there’s a lot of science fiction content musing about what the future will look like. That got me thinking about what a “Day After Tomorrow” movie that dealt with EDA and the semiconductor supply chain might look like. OK, no studio is going to pick up this story, I get it. But for those of us in this business, the p... » read more

Mixing Custom And Standard Parts
By Ed Sperling - 08 Aug, 2013 - Comments: 0

By Ed Sperling The amount of third-party and re-used IP content in an SoC is on the rise, but once a decision to buy vs. make has been made it doesn’t always stay that way. In fact, chipmakers are swinging the pendulum back and forth across a variety of chips, building IP themselves, standardizing on another vendor’s IP, then sometimes rolling it back the other way. The reasons are usua... » read more

Avoiding Pitfalls While Specifying Timing Exceptions
By Various Writers - 08 Aug, 2013 - Comments: 0

Timing exceptions are commonly used to meet timing goals while implementing a design. These exceptions typically cover asynchronous paths like clock domain crossings (CDC) or synchronous paths where timing is either not relevant (e.g., set_false_path command in SDC) or can be relaxed (e.g., set_multicycle_path command in SDC), instructing static timing analysis (STA) and implementation tools to... » read more

IoT Brings Power Awareness Opportunities
By Ann Mutschler - 08 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler Limited only by imagination, the “Internet of Things” (IoT) is breathing new life into many segments of the semiconductor industry that are losing hopes for growth in the SoC market. In virtually any vertical market space, from automotive to consumer, from industrial to networking, one can imagine the potential for what IoT concepts could realize including higher ... » read more

The Week In Review: July 26
By Ed Sperling - 26 Jul, 2013 - Comments: 0

By Ed Sperling Cadence’s Q2 revenue increased 11% to $362 million compared to $326 million in the same period in 2012. On a GAAP basis, net income dropped to $9 million compared with $36 million in 2012, but that decrease was impacted by the cost of recent acquisitions and integration of companies. On a non-GAAP basis, income was $61 million compared with $53 million in Q2 2012. Dassault... » read more

Dealing With New Bottlenecks
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

The Controversial Spec
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler Design sophistication and complexity has made it increasingly difficult to fully specify the expected behavior of a block in an SoC, but this is necessary for design and verification teams. How do you write a “good” and “complete” specification of functionality? It turns out that the discussion of defining what a good and complete specification is and how t... » read more

SEMICON Season And The DAC Dilemma
By Atrenta - 11 Jul, 2013 - Comments: 0

By Mike Gianfagna Amid great fanfare and excitement, SEMICON West started this week. While not as old as DAC (43 years for SEMICON vs. 50 years for DAC), it is a broad and ambitious conference. Billed as “the flagship annual event for the global microelectronics industry,” the conference treats topics such as: Wow, that phrase it taken directly from a SEMCON West email blast, and ... » read more

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