tag: Atrenta

To DVFS Or Not To DVFS
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

I’m in a great position to hear lots of interesting opinions about technology today and this week was no different. During a discussion with Atrenta CTO Bernard Murphy about power and performance tradeoffs, he mentioned that he is not hearing a lot of engineering teams using DVFS (dynamic voltage and frequency scaling) because it creates complications for clock synchronization and makes the d... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

Drowning In Data
By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The old adage, “Be careful what you wish for,” has hit the SoC design market like a 100-year storm. After years of demanding more data to understand what’s going on in a design, engineering teams now have so much data that they’re drowning in it. This is most obvious at advanced process nodes, of course. But it’s also true these days at more mainstream nodes such as... » read more

Watching And Waiting For DFP
By Ann Mutschler - 13 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Although the semiconductor industry has been talking about the need to optimize SoC designs for power for many years, it is safe to say it’s still in the very early stages of the 'Design for Power' approach. That’s not to say that methodologies and tools are not in place. There are actually a number of options available, depending on the level of abstractio... » read more

The Shape Of Things To Come
By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The standard method of designing chips—by shrinking features and turning up the clock frequency—is running out of steam for many companies. It’s too difficult, too expensive, and without a commercially viable new lithography source it may become even more unrealistic for most applications. That certainly doesn’t mean Moore’s Law is ending, but it could become more o... » read more

Hierarchy And Pain Management
By Bernard Murphy - 10 Jun, 2013 - Comments: 0

By Bernard Murphy Hierarchy is unavoidable for any large design. It partitions development and verification complexity into digestible chunks. It enables parallel development on different parts of a system. It promotes reuse. And it provides a graceful method to partition for implementation. And yet, there are times when hierarchy gets in the way. The biggest drawback with hierarchy is that... » read more

Experts At The Table: Nice To Have Vs. Need To Have
By Ed Sperling - 10 Jun, 2013 - Comments: 0

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation. LPE... » read more

The Week In Review: June 7
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling For all the hesitation about moving the Design Automation Conference to Austin, it turns out that Austin has a lot of hardware engineers. In fact they flooded into the conference, turning it into one of the most successful in recent years and setting new records in multiple areas. Even Texas Gov. Rick Perry showed up to see what all the fuss was about. Mentor Graphics added c... » read more

RTL Signoff
By Ed Sperling - 03 Jun, 2013 - Comments: 0

Piyush Sancheti, Atrenta's vice president of product marketing, talks with Low-Power/High-Performance Engineering about where the pain points are in design and why RTL signoff has become so important. [youtube vid=8Ra1_VmzW50] » read more

The Week In Review: May 31
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification pl... » read more

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