The Week In Review: May 31

By Ed Sperling
Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification platform. In addition, Mentor introduced a new version of its embedded software development tool, integrated with its analysis tool and its trace probe. Of particular note in this release are compilation caching for repeated builds, debugger improvements, and automated data collection, analysis and visualization of kernel and application software.

TSMC also certified several of Cadence’s SoC development tools for its 16nm finFETs, including version 0.1 of the design rule manual, the SPICE model tool certification, as well as IP. TSMC also has certified Cadence’s design flow for its 20nm manufacturing process. In addition, PMC adopted Cadence’s physical verification system for signoff in its global design centers.

In addition, TSMC certified a variety of Synopsys’ tools for its 16nm finFET process, including its 3D parasitic extraction technology, as well as double-patterning aware place and route technology, DRC and DPT tools, timing analysis and simulation. Synopsys also extended a multi-year collaboration with ACE Associated Compiler Experts, integrating ACE’s technology into its tools for developing application-specific processors.

Atrenta teamed up with Mentor Graphics to create an interface between Mentor’s emulator and Atrenta’s RTL power estimation. The goal is to greatly speed up the power estimation process, allowing both better performance and the processing of more data. This is an important area because total system power doesn’t always equal the sum of the dynamic power in individual blocks. Atrenta also published a new book about timing constraints.

Dassault Systemes announced its intent to buy Apriso, which makes manufacturing software to synchronize global manufacturing operations. The purchase price is $205 million.

Arteris won a deal with China’s RDA Microelectronics, which is using the Arteris NoC IP for its wireless SoC platforms.

GlobalFoundries will unveil certified design flows developed with Cadence, Mentor Graphics and Synopsys for 20nm LPM and 14nm-XM finFET processes, including support for AMS and digital designs and double patterning. The foundry also will add design flows for 2.5D multi-die integration, also in conjunction with the Big Three EDA vendors.

Japan will become the world’s largest solar revenue market this year, according to IHS iSuppli. The research house also listed the largest automotive ASSP vendors. NXP topped the list for the second year in a row, followed by STMicroelectronics, Renesas and Panasonic.