tag: Atrenta

Roundtable: DAC Retrospective
By Ed Sperling - 13 Jun, 2012 - Comments: 0

Is DAC really a design automation conference, or has it shifted to a design enablement conference due to rising complexity breaking down traditional barriers and silos? Low Power High Performance Engineering talks with Atrenta CTO Bernard Murphy about the changes. [youtube vid=Z_xBaRsC_Hs] » read more

Experts At The Table: IP Subsystems
By Ed Sperling - 29 May, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that co... » read more

New Power Standards Ahead
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ed Sperling Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry. To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with l... » read more

Standards: Too Many or Not Enough?
By Kiran Vittal - 10 May, 2012 - Comments: 0

Many of you are familiar with the Betamax versus VHS format wars in the late 1980s. If you’re not old enough to remember that one, you’ll remember HD DVD versus Blu-ray. In each of these cases, there was a clear winner. Semiconductor design has these format wars, too. The problem is that there is rarely a clear winner and worse, sometimes we miss the standard altogether. There are tw... » read more

Power Becomes Bigger Issue In Stacked Die
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ed Sperling Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die. While power and heat frequently go hand in hand—where there is heat there is almost always power dissipation—t... » read more

Gap Vs. Gap
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable. This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool cha... » read more

The Interconnect Game
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling Having a single bus protocol is something most SoC engineers can only dream about. Reality is often a jumble of protocols determined by the IP they use, which can slow down a design’s progress. The problem stems largely from re-use and legacy IP. While it might be convenient to use only on an AXI standard protocol from ARM, most chips are a combination of IP tied to specif... » read more

Coherency Becomes A Stack Of Issues
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

SoCs Go Mainstream
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling The monolithic ASIC, which has been the bread-and-butter of chipmakers for decades, is giving way to systems on a chip among mainstream chipmakers and at mainstream process nodes. This shift has been overhyped, overpromised and slow to materialize. While SoCs have been common for years in mobile electronics and for high-performance platforms such as gaming consoles, they have... » read more

Whac-A-Mole Anyone?
By Atrenta - 21 Mar, 2012 - Comments: 0

By Mike Gianfagna It started as an arcade game in 1976 (according to Wikipedia), so it’s been around for a while—longer than system-on-chip (SoC) design for sure. It’s essentially a game of futility. A mole pops up and you whack it down with a hammer, only to have another mole pop up elsewhere. Figuratively, you fix one problem and another one pops up. So what does all this have to do wi... » read more

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