tag: Atrenta

The Growing Need For Concurrent Design
By Ed Sperling - 21 Oct, 2010 - Comments: 0

By Ed Sperling The move toward concurrent design is escalating at advanced nodes, driven more by the need to ensure that everything works than previous efforts aimed at efficiency and time-to-market. While the concept has surfaced before in limited doses—engineers and EDA companies have been talking about doing more things simultaneously for the better part of a decade—there are some in... » read more

The Future Of 3D Stacking
By Ed Sperling - 21 Oct, 2010 - Comments: 0

By Ed Sperling Despite concerns about the lack of tools, an unstable process, questionable interconnects, thermal overloads and electrostatic discharge, 3D stacking appears to be making headway. At the very least, lots of companies of all sizes are betting heavily that it will succeed. The first wave, which is expected to start showing up late next year, will likely come from a handful of t... » read more

Bridging IP With Verification Standards
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT -- IEEE 1685, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP. The IP-XACT technical committee has been busy over the past year. Formerly an effor... » read more

Should EDA Remain Coin-Operated?
By Atrenta - 21 Oct, 2010 - Comments: 0

The EDA business model has seen a lot of discussion. Perpetual, time-based, pay as you go, EDA cards, etc., etc. The implications of the chosen business model can have dramatic effects on the overall health of the company involved. Changing the business model can cause mighty companies to topple and weak companies to seem strong (at least for a while). Current trends, such as cloud computing, p... » read more

Experts At The Table: Timing Constraints
By Ed Sperling - 15 Oct, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. Wha... » read more

Experts At The Table: Timing Constraints
By Ed Sperling - 07 Oct, 2010 - Comments: 0

Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. What follows are ex... » read more

Why The Early Edition Was Late
By Atrenta - 23 Sep, 2010 - Comments: 0

By Mike Gianfagna I was a little late with the Early Edition this month. This is kind of embarrassing given the name. Anyone in EDA sales will understand why. It’s the end of the quarter, about a week to go. I’ve been really, really busy. Many EDA companies will book more than 50% of the quarter’s business in the next week. The bean counters have a name for this phenomenon: the ho... » read more

It’s Late Q3 – Do You Know Where Your Chip Is?
By Atrenta - 26 Aug, 2010 - Comments: 0

By Mike Gianfagna Design complexity is increasing. We all get that. But there are other forces at play that may be more significant. Supply chain complexity is also increasing. Outsourcing and off-shoring continue to rise. There exists a general tendency to surrender the fate of your chip to more people. Overlay this situation with the simple fact that in more and more cases the chip defines t... » read more

RTL Fault Coverage Estimation
By Various Writers - 26 Aug, 2010 - Comments: 0

This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require automatic test pattern generation (ATPG) or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort. An important benefit is the means for a user to quickly determine the change... » read more

Experts At The Table: The Power Problem
By Ed Sperling - 23 Jul, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpt... » read more

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