tag: Atrenta

Physical Lint: Physical Quality Metrics For Your RTL
By Mark Baker - 14 May, 2015 - Comments: 0

Why Analyze Physical Metrics at RTL? The quality of the logic structures generated from RTL has a direct impact on the number of design iterations required to close a design. Additionally, the quality of logic structures generated from RTL has a direct impact on design utilization. These trends are illustrated in Figure 1. Essentially, improving the quality of the logic structures in a d... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 14 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

How Do We Push The Limits Of Power?
By Brian Fuller - 14 May, 2015 - Comments: 0

Just how far will we be able to push down power in electronics system design? A bit farther, according to experts presenting at the recent Electronic Design Processes Symposium in Monterey. A combination of materials, techniques, technology and cultural change will get the industry there. During a panel session comparing fully-depleted silicon-on-insulator (FD-SOI) with finFET technology, J... » read more

Security Progress In Some Places, Not Others
By Ed Sperling - 07 May, 2015 - Comments: 0

Security is big business, and it's increasingly part of business done between big businesses in the semiconductor market. The deal that was announced this week between NXP and Qualcomm, adding a secure NFC module to the Snapdragon chip, is certainly good business. But what's really interesting about this arrangement is that it was done between two very prominent companies, which saw a potent... » read more

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Week 45: 7 Weeks To DAC
By Anne Cirkel - 17 Apr, 2015 - Comments: 0

Make sure to download and use the mobile app for #52DAC this year. It will make your time at the conference a lot easier and should even bring you a bit of fun — and a chance to win a new Apple watch. This year the app includes a game called DAC Attack. No, you don’t score by throwing virtual tomatoes at the executive committee, though we can help you rack up points. (More on this in a b... » read more

Stacked Die, Phase Two
By Ed Sperling - 09 Apr, 2015 - Comments: 0

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

UPF 3.0 Moves Toward Ratification
By Ann Mutschler - 09 Apr, 2015 - Comments: 0

[gettech id="31044" t_name="UPF"] (Unified Power Format) 3.0 — the fourth incarnation in 10 years — is moving closer to the IEEE ballot process. Erich Marschner, verification architect at [getentity id="22017" e_name="Mentor Graphics"] and vice chair of the [gettech id="31043" comment="IEEE 1801"] working group, explained the working group is as close as possible to being on schedule for... » read more

Taming Lint With Formal
By Ravindra Aneja - 09 Apr, 2015 - Comments: 1

Designers have been using Linting tools for many years to ensure designs adhere to recommended coding guidelines. Linting tools verify that RTL is written in an unambiguous way to ensure that downstream tools (simulation, synthesis, etc.) do not interpret the code incorrectly, resulting in design, verification, timing or implementation issues. Linting tools take advantage of fast and shallow... » read more

Is Dark Silicon Wasted Silicon?
By Ann Mutschler - 09 Apr, 2015 - Comments: 0

The concept of dark silicon sounds almost mysterious, but it is a simple matter of physics. With advances in technology nodes and the ability to pack more and more transistors on the same die, design engineers are reaching a wall where only a fraction of a design can be powered on due to power and thermal implications. Moreover, the challenges that force this kind of complex power managemen... » read more

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